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  NEC Electronic Components Datasheet  

J599 Datasheet

2SJ599

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J599 pdf
PRELIMINARY DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ599
SWITCHING
P-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The 2SJ599 is P-channel MOS Field Effect Transistor designed
for solenoid, motor and lamp driver.
FEATURES
Low on-state resistance:
RDS(on)1 = 75 mMAX. (VGS = –10 V, ID = –10 A)
RDS(on)2 = 111 mMAX. (VGS = –4.0 V, ID = –10 A)
Low Ciss: Ciss = 1300 pF TYP.
Built-in gate protection diode
TO-251/TO-252 package
ORDERING INFORMATION
PART NUMBER
PACKAGE
2SJ599
TO-251
2SJ599-Z
TO-252
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
–60
Gate to Source Voltage (VDS = 0 V)
VGSS
+20
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
+20
+50
Total Power Dissipation (TC = 25°C) PT 35
Total Power Dissipation (TA = 25°C)
PT 1.0
Channel Temperature
www.DataSSthoereatg4Ue .Tcoemmperature
Single Avalanche Current Note2
Single Avalanche Energy Note2
Tch 150
Tstg –55 to +150
IAS –20
EAS 40
V
V
A
A
W
W
°C
°C
A
mJ
(TO-251)
(TO-252)
Notes 1. PW 10 µs, Duty cycle 1%
2. Starting Tch = 25°C, RG = 25 , VGS = –20 V ¡ 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14644EJ1V0DS00 (1st edition)
Date Published November 2000 NS CP(K)
Printed in Japan
©
2000


  NEC Electronic Components Datasheet  

J599 Datasheet

2SJ599

No Preview Available !

J599 pdf
2SJ599
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
IDSS VDS = 60 V, VGS = 0 V
IGSS VGS = +20 V, VDS = 0 V
Gate Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 10 A
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 10 A
RDS(on)2 VGS = 4.0 V, ID = 10 A
Input Capacitance
Ciss VDS = 10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
ID = 10 A,
Rise Time
tr VGS(on) = 10 V,
Turn-off Delay Time
td(off)
VDD = 30 V,
Fall Time
tf RG = 0
Total Gate Charge
QG ID = 20A,
Gate to Source Charge
QGS VDD= 48 V,
Gate to Drain Charge
QGD
VGS = 10 V
Body Diode Forward Voltage
VF(S-D) IF = 20 A, VGS = 0 V
Reverse Recovery Time
trr IF = 20 A, VGS = 0 V
Reverse Recovery Charge
Qrr di/dt = 100 A / µs
MIN. TYP. MAX.
10
+10
1.5 2.0 2.5
8 16
60 75
78 111
1300
240
100
8
9
52
16
26
5
7
1.0
51
102
UNIT
µA
µA
V
S
m
m
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
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RG = 25
PG
VGS = –20 V 0 V
50
L
VDD
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS ()
0
τ
τ = 1 µs
Duty Cycle 1%
RL
VDD
VGS ()
VGS
Wave Form
10%
0
VDS ()
90%
VDS
VDS 0
Wave Form
td(on)
VGS(on) 90%
10% 10%
90%
tr td(off) tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50
RL
VDD
2 Preliminary Data Sheet D14644EJ1V0DS


Part Number J599
Description 2SJ599
Maker NEC
Total Page 4 Pages
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