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ADC12DS105 Datasheet

(ADC12DSxxx) A/D Converter

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ADC12DS105 pdf
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ADVANCE INFORMATION
February 2007
ADC12DS065/ADC12DS080/ADC12DS095/ADC12DS105
Dual 12-Bit, 65/80/95/105 MSPS A/D Converter with Serial
LVDS outputs
General Description
NOTE: This is Advance Information for products current-
ly in development. ALL specifications are design targets
and are subject to change.
The ADC12DS065, ADC12DS080, ADC12DS095, and AD-
C12DS105 are high-performance CMOS analog-to-digital
converters capable of converting two analog input signals into
12-bit digital words at rates up to 65/80/95/105 Mega Samples
Per Second (MSPS) respectively. The digital outputs are se-
rialized and provided on differential LVDS signal pairs. These
converters use a differential, pipelined architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize power consumption and the external component
count, while providing excellent dynamic performance. A
unique sample-and-hold stage yields a full-power bandwidth
of 1 GHz. The ADC12DS065/080/095/105 may be operated
from a single +3.3V power supply and consumes low power.
A power-down feature reduces the power consumption to
very low levels while still allowing fast wake-up time to full
operation. The differential inputs provide a 2V full scale dif-
ferential input swing. A stable 1.2V internal voltage reference
is provided, or the ADC12DS065/080/095/105 can be oper-
ated with an external 1.2V reference. Output data format
(offset binary versus 2's complement) and duty cycle stabi-
lizer are pin-selectable. The duty cycle stabilizer maintains
performance over a wide range of clock duty cycles.
The ADC12DS065/080/095/105 is available in a 60-lead LLP
package and operates over the industrial temperature range
of −40°C to +85°C.
Features
1 GHz Full Power Bandwidth
Internal sample-and-hold circuit and precision reference
Low power consumption
Clock Duty Cycle Stabilizer
Single +3.3V supply operation
Offset binary or 2's complement output data format
Serial LVDS Outputs
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
Key Specifications
For ADC12DS105
Resolution
Conversion Rate
SNR (fIN = 240 MHz)
SFDR (fIN = 240 MHz)
Full Power Bandwidth
Power Consumption
12 Bits
105 MSPS
67 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
1060 mW (typ)
Applications
High IF Sampling Receivers
Wireless Base Station Receivers
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation
Connection Diagram
© 2007 National Semiconductor Corporation 202117
20211701
www.national.com


National Semiconductor Electronic Components Datasheet

ADC12DS105 Datasheet

(ADC12DSxxx) A/D Converter

No Preview Available !

ADC12DS105 pdf
Block Diagram
Ordering Information
Industrial (−40°C TA +85°C)
ADC12DS065CISQ
ADC12DS080CISQ
ADC12DS095CISQ
ADC12DS105CISQ
20211702
Package
60 Pin LLP
60 Pin LLP
60 Pin LLP
60 Pin LLP
www.national.com
2


Part Number ADC12DS105
Description (ADC12DSxxx) A/D Converter
Maker National Semiconductor
Total Page 30 Pages
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