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National Semiconductor Electronic Components Datasheet

DM5476 Datasheet

Dual Master-Slave J-K Flip-Flops

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DM5476 pdf
June 1989
5476 DM5476 DM7476
Dual Master-Slave J-K Flip-Flops with Clear
Preset and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs The J and
K data is processed by the flip-flop after a complete clock
pulse While the clock is low the slave is isolated from the
master On the positive transition of the clock the data from
the J and K inputs is transferred to the master While the
clock is high the J and K inputs are disabled On the nega-
tive transition of the clock the data from the master is trans-
ferred to the slave The logic state of J and K inputs must
not be allowed to change while the clock is high The data is
transfered to the outputs on the falling edge of the clock
pulse A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs
Features
Y Alternate Military Aerospace device (5476) is available
Contact a National Semiconductor Sales Office Distrib-
utor for specifications
Connection Diagram
Function Table
Dual-In-Line Package
TL F 6528 – 1
Order Number 5476DMQB 5476FMQB
DM5476J DM5476W or DM7476N
See NS Package Number J16A N16E or W16A
Inputs
Outputs
PR CLR CLK J K
Q
Q
LH
HL
LL
HH
HH
HH
HH
X
XX
H
L
X XX L
H
X
XX
H
H
LL
HL
Q0
H
Q0
L
LH
L
H
HH
Toggle
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
e Positive pulse data The J and K inputs must be held constant while
the clock is high Data is transfered to the outputs on the falling edge of the
clock pulse
e This configuration is nonstable that is it will not persist when the preset
and or clear inputs return to their inactive (high) level
Q0 e The output logic level before the indicated input conditions were es-
tablished
Toggle e Each output changes to the complement of its previous level on
each complete active high level clock pulse
C1995 National Semiconductor Corporation TL F 6528
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

DM5476 Datasheet

Dual Master-Slave J-K Flip-Flops

No Preview Available !

DM5476 pdf
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
DM54 and 54
b55 C to a125 C
DM74
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
fCLK
tW
tSU
tH
TA
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 6)
Pulse Width
(Note 6)
Clock High
Clock Low
Preset Low
Clear Low
Input Setup Time (Notes 1 6)
Input Hold Time (Notes 1 6)
Free Air Operating Temperature
DM5476
Min Nom
45 5
2
0
20
47
25
25
0u
0v
b55
Max
55
08
b0 4
16
15
125
DM7476
Min Nom Max
4 75 5
5 25
2
08
b0 4
16
0 15
20
47
25
25
0u
0v
0 70
Units
V
V
V
mA
mA
MHz
ns
ns
ns
C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
Max
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current Max
Input Voltage
VCC e Min II e b12 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max
VCC e Max VI e 5 5V
24
b1 5
34
02 04
1
IIH
High Level Input
VCC e Max
JK
Current
VI e 2 4V
Clock
40
80
Clear
80
Preset
80
IIL
Low Level Input
VCC e Max
JK
Current
VI e 0 4V
Clock
(Note 5)
Clear
b1 6
b3 2
b3 2
Preset
b3 2
IOS Short Circuit
Output Current
VCC e Max
(Note 3)
DM54
DM74
b20
b18
b55
b55
ICC Supply Current
VCC e Max (Note 4)
18
u v u vNote 1 The symbol (
) indicates the edge of the clock pulse is used for reference ( ) for rising edge ( ) for falling edge
Note 2 All typicals are at VCC e 5V TA e 25 C
Note 3 Not more than one output should be shorted at a time
34
Note 4 With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock input is grounded
Note 5 Clear is measured with preset high and preset is measured with clear high
Note 6 TA e 25 C and VCC e 5V
Units
V
V
V
mA
mA
mA
mA
mA
2


Part Number DM5476
Description Dual Master-Slave J-K Flip-Flops
Maker National Semiconductor
Total Page 4 Pages
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