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National Semiconductor Electronic Components Datasheet

DS16EV5110 Datasheet

Video Equalizer

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DS16EV5110 pdf
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PRELIMINARY
March 2007
DS16EV5110
Video Equalizer for DVI, HDMI, and CAT5 Cables
General Description
The DS16EV5110 is a 1.65 Gbps multi-channel equalizer op-
timized for video cable extension applications. It contains
three transition-minimized differential signaling (TMDS) data
channels and one clock channel as commonly found in DVI
and HDMI cables. It provides compensation for skin-effect
losses, a common phenomenon when transmitting video on
commercially available high definition video cables.
The inputs and outputs are fully compliant with DVI 1.0 and
HDMI 1.2a requirements and features programmable levels
of input equalization, providing optimal signal boost and re-
ducing inter-symbol interference. The device supports DC-
coupled data paths providing a wider input common-mode
voltage range and eliminating the need for external coupling
capacitors, reducing solution size and cost.
The clock channel is optimized for clock rates of up to 165
MHz and features a signal detect circuit. The loss of signal
threshold is adjustable through a Serial Management Bus
(SMBus) interface to maximize noise immunity.
The DS16EV5110 also provides support for system power
management via output enable controls. Other controls are
provided via the SMBus enabling customization and opti-
mization for specific applications requirements. These include
programmable features such as output amplitude and boost
control as well as system level diagnostics.
Features
8 levels of equalization settable by 3 pins or through the
SMBus interface
DC-Coupled inputs and outputs
Optimized for operation from 250 Mbps to 1.65 Gbps in
support of 480 I/P, 720 I/P, 1080 I/P or UXGA Resolutions
Two DS16EV5110 devices support DVI/HDMI Dual Link
DVI 1.0 and HDMI 1.2a Compliant TMDS Interface
Clock channel signal detect (LOS)
Enable for power savings standby mode
Serial Management Bus (SMBus) provides control of
boost, output amplitude, enable, and clock channel signal
detect threshold
Low power consumption: 530mW typical, 240mW standby
0.13 UI total jitter at 1.65 Gbps including cable
Single 3.3V power supply
Small 7mm x 7mm, 48-pin leadless LLP package
-40°C to +85°C operating temperature range
Extends TMDS cable reach to:
1. > 40 meters over 24 AWG DVI Cable
2. > 20 meters over 28 AWG DVI Cable
3. > 20 meters over Cat5/Cat5e/Cat6 cables
4. Supports up to 20 meters at 2.25 Gbps over 28 AWG
HDMI cables
Applications
DVI/HDMI Cable Extenders / Switchers
Digital Routers and Switches
Projectors
High Definition Displays
Typical Application
© 2007 National Semiconductor Corporation 202162
20216224
www.national.com


National Semiconductor Electronic Components Datasheet

DS16EV5110 Datasheet

Video Equalizer

No Preview Available !

DS16EV5110 pdf
Pin Descriptions
Pin Name Pin Number I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
C_IN−
C_IN+
1 I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50terminating
2 resistor connects IN+ to VDD and IN- to VDD.
D_IN0−
D_IN0+
4 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50terminating
5 resistor connects IN+ to VDD and IN- to VDD.
D_IN0−
D_IN0+
8 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50terminating
9 resistor connects IN+ to VDD and IN- to VDD.
D_IN0−
D_IN0+
11 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50terminating
12 resistor connects IN+ to VDD and IN- to VDD.
C_OUT-
C_OUT+
36 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
35
D_IN0−
D_IN0+
33 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
32
D_IN0−
D_IN0+
29 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
28
D_IN0−
D_IN0+
26 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
25
Equalization Control
BST_2
BST_1
BST_0
23 I, CMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0,
14 BST_1, and BST_2 are internally pulled high.
37
Device Control
EN 44 I, CMOS Enable Equalizer inputs. When held High, normal operation is selected. When held Low,
standby mode is selected. EN is internally pulled high.
FEB
21 I, CMOS Force External Boost. When held high, the equalizer boost setting is controlled by the BST_
[0:2] pins. When held low, the equalizer boost level is controlled through the SMBus (see
Table 1) control pins. FEB is internally pulled high.
SD 45 O, CMOS Equalizer Clock Channel Signal Detect Output. Produces a high when signal is detect.
POWER
VDD
3, 6, 7,
I, Power VDD = 3.3V ± 10%. VDDpins should be tied to the VDD plane through a low inductance path.
10, 13,
A 0.01µF bypass capacitor should be connected between each VDD pin to the GND planes.
15, 46
GND
22, 24,
27, 30,
31, 34
I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed
Pad
PAD
I, Power Connect to GND. The exposed pad at the center of the package should be connected to the
ground plane of the board to enhance thermal and electrical performance of the package.
Serial Management Bus (SMBus) Interface Control Pins
SDA
SDC
CS
18 I, CMOS Data Input. Internally pulled high.
17 I, CMOS Clock Input. Internally pulled high.
16 I, CMOS Chip select. When held high, the equalizer SMBus register is enabled. When held low, the
equalizer SMBus register is disabled. CS is internally pulled low. CS is internally gated with
SDC.
Other
Reserv
19, 20,
47, 48
Reserved.
NC 43 N/C No Connect.
NC 42 N/C No Connect.
NC 41 N/C No Connect.
NC 40 N/C No Connect.
www.national.com
2


Part Number DS16EV5110
Description Video Equalizer
Maker National Semiconductor
Total Page 16 Pages
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