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  ON Semiconductor Electronic Components Datasheet  

CAV24C128 Datasheet

EEPROM

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CAV24C128 pdf
CAV24C128
128-Kb I2C CMOS Serial
EEPROM
Description
The CAV24C128 is a 128Kb Serial CMOS EEPROM, internally
organized as 16,384 words of 8 bits each.
It features a 64byte page write buffer and supports both the
Standard (100 kHz), Fast (400 kHz) and FastPlus (1 MHz) I2C
protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
OnChip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
Automotive Temperature Grade 1 (40°C to +125°C)
Supports Standard, Fast and FastPlus I2C Protocol
2.5 V to 5.5 V Supply Voltage Range
64Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
8lead SOIC and TSSOP Packages
This Device is PbFree, Halogen Free/BFR Free and RoHS
Compliant*
VCC
SCL
A2, A1, A0
WP
CAV24C128
SDA
VSS
Figure 1. Functional Symbol
* For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
TSSOP8
Y SUFFIX
CASE 948AL
SOIC8
W SUFFIX
CASE 751BD
PIN CONFIGURATION
A0
A1
A2
VSS
1
VCC
WP
SCL
SDA
SOIC (W), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
Pin Name
A0, A1, A2
SDA
SCL
WP
VCC
VSS
PIN FUNCTION
Function
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
November, 2012 Rev. 0
1
Publication Order Number:
CAV24C128/D


  ON Semiconductor Electronic Components Datasheet  

CAV24C128 Datasheet

EEPROM

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CAV24C128 pdf
CAV24C128
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Storage Temperature
65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than 0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than 1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Notes 3, 4) Endurance
1,000,000
Program / Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C
4. This device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specied.)
Symbol
Parameter
Test Conditions
Min Max Units
ICCR
ICCW
ISB
IL
VIL
VIH
VOL
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Read, fSCL = 400 kHz/1 MHz
All I/O Pins at GND or VCC
Pin at GND or VCC
IOL = 3.0 mA
TA = 40°C to +125°C
TA = 40°C to +125°C
0.5
0.7 VCC
1
3
5
2
0.3 VCC
VCC + 0.5
0.4
mA
mA
mA
mA
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specied.)
Symbol
Parameter
Conditions
Max Units
CIN (Note 5)
SDA I/O Pin Capacitance
VIN = 0 V
8 pF
CIN (Note 5)
Input Capacitance (other pins)
VIN = 0 V
6 pF
IWP, IA (Note 6)
WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.3 V
75 mA
50
VIN > VIH
2
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
6. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively
strong; therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pulldown reverts to a weak current source.
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Part Number CAV24C128
Description EEPROM
Maker ON Semiconductor
Total Page 11 Pages
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