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  ON Semiconductor Electronic Components Datasheet  

MC74VHC259 Datasheet

8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

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MC74VHC259 pdf
MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non–addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one–of–eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
The MC74VHC259 input structure provides protectionwwwwh.DeantaSvheoetl4tUa.cgomes
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
High Speed: tPD = 7.6 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 µA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 VCC
15 RESET
14 ENABLE
13 DATA IN
12 Q7
11 Q6
10 Q5
9 Q4
Figure 1. Pin Assignment
http://onsemi.com
MARKING DIAGRAMS
SOIC–16
D SUFFIX
CASE 751B
16 9
VHC259
AWLYYWW
18
TSSOP–16
DT SUFFIX
CASE 948F
SOIC EIAJ–16
M SUFFIX
CASE 966
16 9
VHC259
AWLYWW
1
8
16 9
VHC259
ALYW
18
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC259D
SOIC–16 48 Units/Rail
MC74VHC259DR2 SOIC–16 2500 Units/Reel
MC74VHC259DT TSSOP–16 96 Units/Rail
MC74VHC259DTR2 TSSOP–16 2500 Units/Reel
MC74VHC259M
SOIC
EIAJ–16
50 Units/Rail
SOIC
MC74VHC259MEL EIAJ–16 2000 Units/Reel
© Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1
Publication Order Number:
MC74VHC259/D


  ON Semiconductor Electronic Components Datasheet  

MC74VHC259 Datasheet

8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

No Preview Available !

MC74VHC259 pdf
MC74VHC259
A0 1
ADDRESS
INPUTS
A1
2
A2 3
13
DATA IN
4 Q0
5 Q1
6 Q2
7 Q3
9 Q4
10 Q5
11 Q6
12 Q7
NONINVERTING
OUTPUTS
RESET
ENABLE
15
14
PIN 16 = VCC
PIN 8 = GND
Figure 2. Logic Diagram
A0 1
A1 2
A2 3
13
14
15
BIN/OCT
10
4 Q0
2 1 5 Q1
4 2 6 Q2
3 7 Q3
4 8 Q4
ID 5 10 Q5
EN 6 11 Q6
R 7 12 Q7
A0 1
A1 2
A2 3
13
14
15
DMUX
00
4 Q0
G
0
7
2
1
2
5 Q1
6 Q2
3 7 Q3
4 8 Q4
ID 5 10 Q5
EN 6 11 Q6
R 7 12 Q7
Figure 3. IEC Logic Symbol
LATCH SELECTION TABLE
Address Inputs
CBA
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
Latch
Addressed
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MODE SELECTION TABLE
Enable Reset
Mode
L H Addressable Latch
H H Memory
L L 8–Line Demultiplexer
H L Reset
http://onsemi.com
2


Part Number MC74VHC259
Description 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
Maker ON Semiconductor
Total Page 8 Pages
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