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  ON Semiconductor Electronic Components Datasheet  

MTD10N10EL Datasheet

Power Field Effect Transistor DPAK

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MTD10N10EL pdf
MTD10N10EL
TMOS E−FET
Power Field Effect Transistor
DPAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This advanced TMOS E−FET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
Features
Avalanche Energy Specified
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Pb−Free Package is Available
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) www.DataSheet4U.com
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage − Continuous
Non−Repetitive (tp 10 ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (tp 10 ms)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
100 Vdc
100 Vdc
±15 Vdc
±20 Vpk
10 Adc
6.0
35 Apk
40 W
0.32 W/°C
1.75 W
−55 to °C
150
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 10 Apk,
L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Temperature for Soldering
Purposes, 1/8from case for 10 sec
EAS mJ
50
RθJC
RθJA
RθJA
TL
°C/W
3.13
100
71.4
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using minimum recommended pad
size.
2. When surface mounted to an FR4 board using 0.5 sq in pad size.
http://onsemi.com
VDSS
100 V
RDS(ON) TYP
0.22 W
ID MAX
10 A
N−Channel
D
G
S
MARKING DIAGRAM & PIN ASSIGNMENTS
4 Gate 1
YWW
12
3
DPAK
CASE 369C
Drain 2
10N
10ELG
Source 3
(Surface Mount)
STYLE 2
4
Drain
10N10EL
Y
WW
G
= Device Code
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
MTD10N10ELT4 DPAK 2500 Tape & Reel
MTD10N10ELT4G DPAK 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 3
1
Publication Order Number:
MTD10N10EL/D


  ON Semiconductor Electronic Components Datasheet  

MTD10N10EL Datasheet

Power Field Effect Transistor DPAK

No Preview Available !

MTD10N10EL pdf
MTD10N10EL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (VGS = 5.0 Vdc, ID = 5.0 Adc)
Drain−to−Source On−Voltage
(VGS = 5.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 50 Vdc, ID = 10 Adc,
VGS = 5.0 Vdc, RG = 9.1 W)
Fall Time
Gate Charge (See Figure 8)
(VDS = 80 Vdc, ID = 10 Adc,
VGS = 5.0 Vdc)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(IS = 10 Adc, VGS = 0 Vdc)
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperature.
Symbol
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
trr
ta
tb
QRR
LD
LS
Min Typ Max Unit
100 −
− 115
Vdc
− mV/°C
mAdc
− − 10
− − 100
− − 100 nAdc
Vdc
1.0 1.45 2.0
− 4.0 − mV/°C
− 0.17 0.22 W
Vdc
− 1.85 2.6
− − 2.3
2.5 7.9
− mhos
741 1040
pF
− 175 250
− 18.9 40
− 11 20 ns
− 74 150
− 17 30
− 38 80
− 9.3 15 nC
− 2.56 −
− 4.4 −
− 4.66 −
Vdc
− 0.98 1.6
− 0.898 −
− 124.7 −
ns
− 86 −
− 38.7 −
− 0.539 −
mC
nH
− 4.5 −
nH
− 7.5 −
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2


Part Number MTD10N10EL
Description Power Field Effect Transistor DPAK
Maker ON Semiconductor
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