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  ON Semiconductor Electronic Components Datasheet  

N01S830BA Datasheet

1 Mb Ultra-Low Power Serial SRAM

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N01S830BA pdf
N01S830HA, N01S830BA
1 Mb Ultra-Low Power
Serial SRAM
Standard SPI Interface and Multiplex
DUAL and QUAD Interface
Overview
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 1 Mb serially accessed
Static Random Access Memory, internally organized as 128 K words
by 8 bits. The devices are designed and fabricated using
ON Semiconductor’s advanced CMOS technology to provide both
high-speed performance and low power. The devices operate with a
single chip select (CS) input and use a simple Serial Peripheral
Interface (SPI) protocol. In SPI mode, a single data-in (SI) and
data-out (SO) line is used along with the clock (SCK) to access data
within the device. In DUAL mode, two multiplexed data-in/data-out
(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed
data-in/data-out (SIO0-SIO3) lines are used with the clock to access
the memory. The devices can operate over a wide temperature range of
−40°C to +85°C (+125°C for E−Temp) and are available in a 8-lead
TSSOP package. The N01S830xA device has two different variations,
a HOLD version that allows communication to the device to be paused
and a battery back-up (BBU) version to be used with a battery to retain
data when power is lost.
Features
Power Supply Range: 2.5 to 5.5 V
Very Low Typical Standby Current < 4 mA at +85°C
Very Low Operating Current < 10 mA
Simple Serial Interface
Single-bit SPI Access
DUAL-bit and QUAD-bit SPI-like Access
Flexible Operating Modes
Word Mode
Page Mode
Burst Mode (Full Array)
High Frequency Read and Write Operation
Clock Frequency up to 20 MHz
Functional Options
HOLD Pin for Pausing Operation
VBAT Pin for Battery−Back up
Built-in Write Protection (CS High)
High Reliability
Unlimited Write Cycles
Temperature Ranges Supported
Industrial (I): TA = −40°C to +85°C
Automotive (E): TA = −40°C to +125°C
These Devices are Pb−Free and are RoHS Compliant
Green TSSOP
www.onsemi.com
TSSOP8 3x4.4
CASE 948BH
PACKAGE CONFIGURATION
CS
SO / SIO1
NC / SIO2
VSS
18
27
36
45
HOLD Version
VCC
HOLD / SIO3
SCK
SI / SIO0
CS
SO / SIO1
NC
VSS
18
27
36
45
BBU Version
VCC
VBAT
SCK
SI / SIO0
ORDERING INFORMATION
Device
Package
Shipping
N01S830HAT22I
N01S830BAT22I
N01S830HAT22IT
N01S830BAT22IT
TSSOP−8
(Pb−Free)
100 Units / Tube
TSSOP−8
(Pb−Free)
3000 / Tape
& Reel
N01S830HAT22E
N01S830BAT22E
TSSOP−8
(Pb−Free)
100 Units / Tube
N01S830HAT22ET TSSOP−8
N01S830BAT22ET (Pb−Free)
3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 2
1
Publication Order Number:
N01S830HA/D


  ON Semiconductor Electronic Components Datasheet  

N01S830BA Datasheet

1 Mb Ultra-Low Power Serial SRAM

No Preview Available !

N01S830BA pdf
N01S830HA, N01S830BA
Table 1. DEVICE OPTIONS
Device / Part Number
N01S830HAT22
N01S830BAT22
Power Supply
HV 2.5 V − 5.5 V
HV 2.5 V − 5.5 V
Table 2. PIN NAMES
CS
SCK
Pin Name
SI / SIO0
SO / SIO1
NC / SIO2
HOLD / SIO3
VBAT
VCC
VSS
Speed
20 MHz for I−Temp,
16 MHz E−Temp
20 MHz for I−Temp,
16 MHz E−Temp
Package
TSSOP−8
Temperature
Range
I, E
Function
HOLD
TSSOP−8
I, E BBU − Battery Back-up
Pin Function
Chip Select
Serial Clock
Data Input − SPI mode
Data Input/Output 0 − DUAL and QUAD mode
Data Output − SPI mode
Data Input/Output 1 − DUAL and QUAD mode
No Connect − SPI and DUAL mode
Data Input/Output 2 − QUAD mode
HOLD Version
HOLD Input − SPI and DUAL mode
Data Input/Output 3 − QUAD mode
BBU Version
Battery Supply − SPI and DUAL mode
Power
Ground
SCK
CS
SI / SIO0
SO / SIO1
SIO2
HOLD / SIO3
(HOLD Version)
Interface
Circuitry
Decode
Logic
Control
Logic
Data Flow
Circuitry
SRAM
Array
VBAT
(BBU Version)
Battery Controls
Figure 1. Functional Block Diagram
Table 3. CONTROL SIGNAL DESCRIPTIONS
Signal
Mode
Used
Name
Description
CS All Chip Select A low level selects the device and a high level puts the device in standby mode. If CS is brought
high during a program cycle, the cycle will complete and then the device will enter standby mode.
When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence
being started.
SCK
All Serial Clock Synchronizes all activities between the memory and controller. All incoming addresses, data and
instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of
SCK.
SI SPI Serial Data In Receives instructions, addresses and data on the rising edge of SCK.
SO SPI Serial Data Out Data is transferred out after the falling edge of SCK.
www.onsemi.com
2


Part Number N01S830BA
Description 1 Mb Ultra-Low Power Serial SRAM
Maker ON Semiconductor
Total Page 13 Pages
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