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  ON Semiconductor Electronic Components Datasheet  

NB3N106K Datasheet

3.3V Differential 1:6 Fanout Clock Driver

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NB3N106K pdf
NB3N106K
3.3V Differential 1:6 Fanout
Clock Driver with HCSL
Outputs
Description
The NB3N106K is a differential 1:6 Clock fanout buffer with
Highspeed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N106K is designed
with HCSL PCI Express clock distribution and FBDIMM
applications in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL
signals per Figures 7, 8, and 9. Singleended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external Vth
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N106K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N106K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333, and
400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair
0.1 ps Typical Integrated Phase Jitter RMS
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Typical HCSL Output Levels (700 mV PeaktoPeak)
LVDS Output Levels with Interface Termination
These are PbFree Devices*
Applications
Clock Distribution
PCIe, II, III
Networking and Communications
High End Computing
End Products
Servers
FBDIMM Memory Cards
Ethernet Switch/Routers
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
QFN24
MN SUFFIX
CASE 485L
MARKING DIAGRAM*
NB3N
106K
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
Q0
Q0
Q1
CLK Q1
CLK
VTCLK
VCC
GND
IREF
RREF
Q4
Q4
Q5
Q5
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 5
1
Publication Order Number:
NB3N106K/D


  ON Semiconductor Electronic Components Datasheet  

NB3N106K Datasheet

3.3V Differential 1:6 Fanout Clock Driver

No Preview Available !

NB3N106K pdf
NB3N106K
Exposed Pad (EP)
IREF 1
VTCLK 2
CLK 3
CLK 4
VTCLK 5
GND 6
24 23 22 21 20 19
NB3N106K
7 8 9 10 11 12
18 VCC
17 Q2
16 Q2
15 Q3
14 Q3
13 VCC
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1 IREF
Use the IREF pin to set the output drive. Connect a 475 W RREF resistor from the
IREF pin to GND to produce 2.6 mA of IREF current. A current mirror multiplies
IREF by a factor of 5.4x to force 14 mA through a 50 W output load. See Figures 6
and 12.
2, 5
VTCLK,
Internal 50 W Termination Resistor connection Pins. In the differential configuration
VTCLK
when the input termination pins are connected to the common termination voltage,
and if no signal is applied then the device may be susceptible to selfoscillation.
3 CLK LVPECL, Clock (TRUE) Input
HCSL, LVDS
Input
4 CLK LVPECL, Clock (INVERT) Input
HCSL, LVDS
Input
8, 10, 14, 16, 20,
22
Q[50]
HCSL or
Output (INVERT) (Note 1)
LVDS (Note 1)
Output
9, 11, 15, 17, 21,
23
Q[50]
HCSL or
LVDS
(Note 1)
Output
Output (TRUE) (Note 1)
6
GND
Supply Ground. GND pin must be externally connected to power supply to
guarantee proper operation.
7, 12, 13, 18, 19,
24
VCC
Positive Voltage Supply pin. VCC pin must be externally connected to a power
supply to guarantee proper operation.
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a sufficient heatsinking conduit for proper thermal
operation and electrically connected to the circuit board ground (GND).
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
http://onsemi.com
2


Part Number NB3N106K
Description 3.3V Differential 1:6 Fanout Clock Driver
Maker ON Semiconductor
Total Page 10 Pages
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