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  ON Semiconductor Electronic Components Datasheet  

NB3N111K Datasheet

3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K pdf
NB3N111K
3.3V Differential 1:10
Fanout Clock Driver with
HCSL Outputs
Description
The NB3N111K is a differential 1:10 Clock fanout buffer with
Highspeed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N111K is designed
with PCI Express HCSL clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL
signals per Figures 7, 8, and 9. Singleended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external Vth
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS
receivers when terminated per Figure 11.
The NB3N111K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N111K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, or 400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair
0.1 ps Typical RMS Additive Phase Jitter
LVDS Output Levels Optional with Interface Termination
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Typical HCSL Output Levels (700 mV PeaktoPeak)
LVDS Output Levels with Interface Termination
These are PbFree Devices
Applications
Clock Distribution
PCIe I, II, III
Networking
High End Computing
Routers
End Products
Servers
FBDIMM Memory Card
© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 5
1
http://onsemi.com
1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
1
NB3N
111K
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
CLK
CLK
VTCLK
VCC
GND
IREF
RREF
Q0
Q0
Q1
Q1
Q8
Q8
Q9
Q9
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Publication Order Number:
NB3N111K/D


  ON Semiconductor Electronic Components Datasheet  

NB3N111K Datasheet

3.3V Differential 1:10 Fanout Clock Driver

No Preview Available !

NB3N111K pdf
NB3N111K
Exposed Pad (EP)
32 31 30 29 28 27 26 25
IREF 1
VTCLK 2
CLK 3
CLK 4
VTCLK 5
Q9 6
Q9 7
GND 8
NB3N111K
24 VCC
23 Q3
22 Q3
21 Q4
20 Q4
19 Q5
18 Q5
17 VCC
9 10 11 12 13 14 15 16
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O
Description
1 IREF
Use the IREF pin to set the output drive. Connect a 475 W RREF
resistor from the IREF pin to GND to produce 2.6 mA of IREF current. A
current mirror multiplies IREF by a factor of 5.4x to force 14 mA through
a 50 W output load. See Figures 6 and 12.
2, 5 VTCLK,
VTCLK
Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the
common termination voltage, and if no signal is applied then the device
may be susceptible to selfoscillation.
3 CLK LVPECL, HCSL, Clock and Data (TRUE) Input
LVDS Input
4 CLK LVPECL, HCSL, Clock and Data (INVERT) Input
LVDS Input
6, 10, 12, 14, 18, 20,
22, 26, 28, 30
Q[90]
HCSL or LVDS
(Note 1) Output
Output (INVERT) (Note 1)
7, 11, 13, 15, 19, 21,
23, 27, 29, 31
Q[90]
HCSL or LVDS
(Note 1) Output
Output (TRUE) (Note 1)
8 GND Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
9, 16, 17, 24, 25, 32
VCC
Positive Voltage Supply pin. VCC pins must be externally connected to a
power supply to guarantee proper operation.
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation and electrically connected to the circuit board
ground (GND).
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
http://onsemi.com
2


Part Number NB3N111K
Description 3.3V Differential 1:10 Fanout Clock Driver
Maker ON Semiconductor
Total Page 9 Pages
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