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  ON Semiconductor Electronic Components Datasheet  

NB3N51032 Datasheet

Dual HCSL/LVDS Clock Generator

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NB3N51032 pdf
NB3N51032
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL/LVDS
Clock Generator
The NB3N51032 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
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25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 10). The NB3N51032 provides selectable
spread options of −0.5% and −0.75% for applications demanding low
Electromagnetic Interference (EMI) as well as optimum performance
with no spread option.
Features
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
MARKING
DIAGRAM
16 16
NB3N
1
TSSOP−16
DT SUFFIX
1032
ALYWG
1G
CASE 948F
A = Assembly Location
L = Wafer Lot
External Loop Filter is Not Required
HCSL Differential Output or LVDS with Proper Termination
Four Selectable Multipliers of the Input Frequency
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Output Enable with Tri−State Outputs
PCIe Gen 1, Gen 2, Gen 3 Compliant
Spread of −0.5%, −0.75% and No Spread
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Phase Noise: @ 100 MHz
Offset Noise Power
Applications
Networking
100 Hz −88 dBc/Hz
Consumer
1 kHz −118 dBc/Hz
10 kHz −131 dBc/Hz
100 kHz −132 dBc/Hz
1 MHz −144 dBc/Hz
10 MHz −155 dBc/Hz
Typical Period Jitter RMS of 1.5 ps
Computing and Peripherals
Industrial Equipment
PCIe Clock Generation Gen 1, Gen 2 and Gen 3
Gigabit Ethernet
FB DIMM
Operating Supply Voltage Range 3.3 V ±5%
Industrial Temperature Range −40°C to +85°C
Functionally Compatible with IDT557−03,
IDT5V41065, IDT5V41235 with enhanced performance
These are Pb−Free Devices
End Products
Switch and Router
Set Top Box, LCD TV
Servers, Desktop Computers
Automated Test Equipment
VDD SS0 SS1
X1/CLK
Spread Spectrum
Circuit
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
Charge
Pump
BN
VCO
HCSL
Output
HCSL
Output
CLK0
CLK0
CLK1
CLK1
VDD = VDDODA = VDDXD
GND = GNDODA = GNDXD
GND
S0 S1
Figure 1. NB3N51032 Simplified Logic Diagram
OE IREF
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 2
1
Publication Order Number:
NB3N51032/D


  ON Semiconductor Electronic Components Datasheet  

NB3N51032 Datasheet

Dual HCSL/LVDS Clock Generator

No Preview Available !

NB3N51032 pdf
NB3N51032
S0 1
16 VDDXD
S1 2
15 CLK0
SS0 3
14 CLK0
X1/CLK
X2
4
5
13 GNDODA
12 VDDODA
OE 6
11 CLK1
GNDXD
SS1
7
8
10 CLK1
9 IREF
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Symbol
I/O
1 S0
Input
2 S1
Input
3 SS0
Input
4 X1/CLK
Input
5 X2
Input
6 OE
Input
7 GNDXD Power Supply
8 SS1
Input
9 IREF
Output
10
CLK1
HCSL or
LVDS Output
11
CLK1
HCSL or
LVDS Output
12 VDDODA Power Supply
13 GNDODA Power Supply
14
CLK0
HCSL or
LVDS Output
15
CLK0
HCSL or
LVDS Output
16 VDDXD Power Supply
Description
LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output
select table 2 for details.
LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output
select Table 2 for details.
LVTTL/LVCMOS Spread select input 0. Internal pullup resistor to VDDXD. See Spread se-
lection Table 3 for details.
Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock.
Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.
Output enable tri−states output when connected to GND. Internal pullup resistor to VDDXD.
Ground 0 V. This pin provides GND return path for the device.
LVTTL/LVCMOS Spread select input 1. Internal pullup resistor to VDDXD. See Spread se-
lection Table 3 for details.
Output current reference pin. Precision resistor (typ. 475 W) is connected to set the output
current.
Inverted clock output. (For LVDS levels see Figure 10)
Noninverted clock output. (For LVDS levels see Figure 10)
Positive supply voltage pin connected to +3.3 V supply voltage.
Ground 0 V. These pins provide GND return path for the devices.
Inverted clock output. (For LVDS levels see Figure 10)
Noninverted clock output. (For LVDS levels see Figure 10)
Positive supply voltage pin connected to +3.3 V supply voltage.
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2


Part Number NB3N51032
Description Dual HCSL/LVDS Clock Generator
Maker ON Semiconductor
Total Page 13 Pages
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