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NB6L14 Datasheet

Differential 1:4 LVPECL Fanout Buffer

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NB6L14 pdf
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NB6L14
2.5 V/3.3 V 3.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
MultiLevel Inputs with Internal Termination
Description
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL fanout buffer.
The differential inputs incorporate internal 50 W termination resistors
that are accessed through the VT pin. This feature allows the NB6L14
to accept various logic standards, such as LVPECL, LVCMOS,
LVTTL, CML, or LVDS logic levels. The VREF_AC reference output
can be used to rebias capacitorcoupled differential or singleended
input signals. The 1:4 fanout design was optimized for low output
skew applications.
The NB6L14 is a member of the ECLinPS MAXfamily of high
performance clock and data products.
Features
Maximum Input Clock Frequency > 2.5 GHz, Typical
< 20 ps Within Device Output Skew
330 ps Typical Propagation Delay
145 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 720 mV Amplitude, Typical
LVPECL Mode Operating Range: VCC = 2.375 V to 3.63 V with
GND = 0 V
Internal 50 W Input Termination Resistors Provided
VREF_AC Reference Output Voltage
40°C to +85°C Ambient Operating Temperature
Available in 3 mm x 3 mm 16 Pin QFN
These are PbFree Devices
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
DQ
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 Rev. 0
1
Publication Order Number:
NB6L14/D


  ON Semiconductor Electronic Components Datasheet  

NB6L14 Datasheet

Differential 1:4 LVPECL Fanout Buffer

No Preview Available !

NB6L14 pdf
NB6L14
Q0 Q0 VCC GND
16 15 14 13
Exposed Pad (EP)
Q0
/Q0
Q1 1
Q1 2
Q2 3
12 IN
11 VT
10 VREF_AC
IN
VT
/IN
50 W
50 W
Q1
/Q1
Q2
Q2 4
9 IN
EN
DQ
/Q2
5 678
Q3 Q3 VCC EN
Figure 2. QFN16 Pinout
(Top View)
VREF_AC
CLK Q3
/Q3
Figure 3. Logic Diagram
Table 1. EN TRUTH TABLE
IN
IN
EN
Q0:Q3
Q0:Q3
01
10
xx
+ = On next negative transition of the input signal (IN).
x = Don’t care.
1
1
0
01
10
0+ 1+
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 Q1 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to
VCC–2.0 V.
2
Q1
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
3 Q2 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to
VCC – 2.0 V.
4
Q2
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
5 Q3 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to
VCC – 2.0 V.
6
Q3
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
7 VCC
Positive Supply Voltage
8 EN LVTTL/LVCMOS Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML,
Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
LVDS, HSTL
10 VREF_AC
Output Voltage Reference for capacitorcoupled inputs, only.
11 VT
Internal 100 W centertapped Termination Pin for IN and IN.
12
IN
LVPECL, CML,
Noninverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
LVDS, HSTL
13 GND
Negative Supply Voltage
14 VCC
Positive Supply Voltage
15 Q0 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to
VCC–2.0 V.
16
Q0
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC–2.0 V.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heatsinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN inputs, then the device will be susceptible to selfoscillation.
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2


Part Number NB6L14
Description Differential 1:4 LVPECL Fanout Buffer
Maker ON Semiconductor
Total Page 10 Pages
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