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  ON Semiconductor Electronic Components Datasheet  

NB6N14S Datasheet

Differential Input to LVDS Fanout Buffer/Translator

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NB6N14S pdf
NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to VCC 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or singleended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16QFN
package. Application notes, models, and support documentation are
available at www.onsemi.com.
The NB6N14S is a member of the ECLinPS MAXt family of high
performance products.
Features
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum RMS Clock Jitter
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Typically 10 ps Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
VREF_AC Reference Output
TIA/EIA 644 Compliant
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are PbFree Devices
Device DDJ = 10 ps
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1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6N
14S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
VT
/IN
50 W
50 W
EN
(LVTTL/CMOS)
VREF_AC
DQ
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2231 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2007
January, 2007 Rev. 3
1
Publication Order Number:
NB6N14S/D


  ON Semiconductor Electronic Components Datasheet  

NB6N14S Datasheet

Differential Input to LVDS Fanout Buffer/Translator

No Preview Available !

NB6N14S pdf
NB6N14S
Q0 Q0 VCC GND
16 15 14 13
Exposed Pad (EP)
Q1 1
Q1 2
Q2 3
Q2 4
NB6N14S
12 IN
11 VT
10 VREF_AC
9 IN
5 678
Q3 Q3 VCC EN
Figure 3. NB6N14S Pinout, 16pin QFN (Top View)
Table 1. TRUTH TABLE
IN IN EN Q
01 1 0
10 1 1
xx
0 0 (Note 1)
1. On next transition of the input signal (IN).
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 Q1
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3 Q2
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 Q3
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6 Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7 VCC
Positive Supply Voltage.
8 EN LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 19. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10 VREF_AC
LVPECL Output
The VREF_AC reference output can be used to rebias capacitorcoupled
differential or singleended input signals. For the capacitorcoupled IN and/or
INb inputs, VREF_AC should be connected to the VT pin and bypassed to
ground with a 0.01 mF capacitor.
11 VT
LVPECL Output
Internal 100 W Centertapped Termination Pin for IN and IN
12
IN
LVPECL, CML, LVDS
Noninverted Differential Input. (Note 2)
13 GND
14 VCC
15 Q0
LVDS Output
Negative Supply Voltage.
Positive Supply Voltage.
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16 Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to selfoscillation.
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2


Part Number NB6N14S
Description Differential Input to LVDS Fanout Buffer/Translator
Maker ON Semiconductor
Total Page 10 Pages
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