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UPA2521 Datasheet

MOS FIELD EFFECT TRANSISTOR

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UPA2521 pdf
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA2521
N-CHANNEL MOS FET
FOR SWITCHING
DESCRIPTION
The μ PA2521 is N-channel MOS Field Effect Transistor
designed for DC/DC converter and power management
applications of portable equipments.
PACKAGE DRAWING (Unit: mm)
2.9±0.1
0.65
8
5
A
0.17±0.05
FEATURES
Low on-state resistance
RDS(on)1 = 16.5 mΩ MAX. (VGS = 10 V, ID = 8.0 A)
RDS(on)2 = 25 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A)
Built-in gate protection diode
Small and surface mount package (8-pin VSOF (2429))
Pb-free (This product does not contain Pb in external electrode
and other parts.)
0 to 0.025
1
0.32±0.05
4
0.05 M S A
1, 2, 3 : Source
4 : Gate
5, 6, 7, 8: Drain
S
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation Note2
Total Power Dissipation (PW = 5 sec) Note2
ID(DC)
ID(pulse)
PT1
PT2
±8
±32
1.0
2.2
A
A
W
W
Channel Temperature
Tch 150 °C
Storage Temperature
Single Avalanche Current Note3
Single Avalanche Energy Note3
Tstg 55 to +150 °C
IAS 8 A
EAS 6.4 mJ
Notes 1. PW 10 μs, Duty Cycle 1%
2. Mounted on FR-4 board of 25.4 mm x 25.4 mm x 0.8 mmt
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 0 V, L = 100 μH
EQUIVALENT CIRCUIT
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G19187EJ1V0DS00 (1st edition)
Date Published March 2008 NS
Printed in Japan
2008


Renesas Electronics Components Datasheet

UPA2521 Datasheet

MOS FIELD EFFECT TRANSISTOR

No Preview Available !

UPA2521 pdf
μ PA2521
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
Zero Gate Voltage Drain Current
IDSS
Gate Leakage Current
IGSS
Gate to Source Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Gate Resistance
RG
VDS = 30 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 4.0 A
VGS = 10 V, ID = 8.0 A
VGS = 4.5 V, ID = 4.0 A
VDS = 15 V,
VGS = 0 V,
f = 1 MHz
VDD = 15 V, ID = 4.0 A,
VGS = 10 V,
RG = 10 Ω
VDD = 15 V,
VGS = 5 V,
ID = 8 A
IF = 8 A, VGS = 0 V
IF = 8 A, VGS = 0 V,
di/dt = 100 A/μs
f = 1 MHz
1.5
3.2
Note Pulsed
TYP.
12
17
780
170
61
9.2
3.8
31
4.8
7.6
2.6
2.4
0.82
24
17
1.6
MAX.
10
±10
2.5
16.5
25
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Ω
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet G19187EJ1V0DS


Part Number UPA2521
Description MOS FIELD EFFECT TRANSISTOR
Maker Renesas
Total Page 5 Pages
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