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STMicroelectronics Electronic Components Datasheet

STLS2F02 Datasheet

High performance 64-bit superscalar MIPS microprocessor

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STLS2F02 pdf
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STLS2F02
Loongson 2F
high performance 64-bit superscalar MIPS® microprocessor
Preliminary Data
Features
64-bit superscalar architecture
900 MHz clock frequency
Single/double precision floating-point units
New streaming multimedia instruction set
support (SIMD)
64 Kbyte instruction cache, 64 Kbyte data
cache, on-chip 512 Kbyte unified L2 cache
On chip DDR2-667 and PCI-X controller
4 W @ 900 MHz power consumption:
– Best in class for power management
– Voltage/frequency scaling
– Standby mode support
– L2 cache disable/enable option
Leading edge 90 nm process technology
27x27 heat spreader flip-chip BGA package
MIPS based (compatible with MIPSIII)
instruction set
Description
The STLS2F02 is a MIPS based 64-bit
superscalar microprocessor, able to issue four
instructions per clock cycle among six functional
units: two integer, two single/double-precision
floating-point, one 64-bit SIMD and one load/store
unit.
The micro architecture is organized with nine
stages of pipeline and support of dynamic branch
prediction.
HFCBGA452 (27x27x2.9mm)
The memory hierarchy is composed by the first
level of 64 Kbyte 4-way set associative caches for
instructions and data, the second level of
512 Kbyte unified 4-way set associative cache
and the memory management unit with table
lookside buffer.
The Loongson microprocessor family is the
outcome of a successful collaboration started in
2004 between STMicroelectronics and the
Institute of Computing Technology, part of the
Chinese Academy of Science. Loongson
microprocessors were co-developed by
STMicroelectronics and the Institute of
Computing Technology to address all the
applications requiring high level of performance
and low power dissipation.
Compared to the STLS2E02 processor, the
STLS2F02 has an enhanced architecture
providing higher performances, reduced power
consumption, integrated DDR2 memory controller
and PCI-X bus interface.
Table 1.
Device summary
Order code
STLS2F02
Package
HFCBGA452 (27x27x2.9 mm)
Packing
Tray
August 2008
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/49
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STMicroelectronics Electronic Components Datasheet

STLS2F02 Datasheet

High performance 64-bit superscalar MIPS microprocessor

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STLS2F02 pdf
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Contents
STLS2F02
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 PCI bus interface signal components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 DDR2 SDRAM interface signal components . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Initialization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7 JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8 Test and control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10 Supply and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 IO bus interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 PCI interface characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Host and agent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 PCI bus arbitrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 System interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 Single processor system connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.2 Multiprocessor system connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Local bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 DDR2 SDRAM controller interface description . . . . . . . . . . . . . . . . . . 21
4.1 DDR2 SDRAM controller features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 DDR2 SDRAM parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1 Memory initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.2 Parameter descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4.3 Parameter formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/49


Part Number STLS2F02
Description High performance 64-bit superscalar MIPS microprocessor
Maker STMicroelectronics
Total Page 30 Pages
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