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  Samsung Electronic Components Datasheet  

K7N403601M Datasheet

(K7N401801M / K7N403601M) 128Kx36 & 256Kx18 Pipelined NtRAM-TM

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K7N403601M pdf
K7N403601M
K7N401801M
128Kx36 & 256Kx18 Pipelined NtRAMTM
wwwD.DoatcaSuhmeete4Un.ctomTitle
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75
2. Changed DC condition at Icc and parameters
ISB1 ; from 10mA to 30mA,
ISB2 ; from 10mA to 30mA.
0.2 Add VDDQ Supply voltage( 2.5V I/O )
0.3 Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O.
1.0 Final spec Release.
2.0 Remove VDDQ Supply voltage( 2.5V I/O )
3.0 Add VDDQ Supply voltage( 2.5V I/O )
Draft Date
July.06. 1998
Oct. 10 . 1998
Dec. 10. 1998
Dec. 23. 1998
Jan. 29. 1999
Feb. 25. 1999
May. 13. 1999
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - May 1999
Rev 3.0


  Samsung Electronic Components Datasheet  

K7N403601M Datasheet

(K7N401801M / K7N403601M) 128Kx36 & 256Kx18 Pipelined NtRAM-TM

No Preview Available !

K7N403601M pdf
K7N403601M
K7N401801M
128Kx36 & 256Kx18 Pipelined NtRAMTM
www1.D2a8taKShxee3t46U.&com256Kx18-Bit Pipelined NtRAMTM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention
Α interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A Package.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -15 -13 -10 Unit
tCYC 6.7 7.5 10 ns
tCD 3.8 4.2 5.0 ns
tOE 3.8 4.2 5.0 ns
GENERAL DESCRIPTION
The K7N403601M and K7N401801M are 4,718,592 bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incomming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge trigered output register and then released to
the output bufferes at the next rising edge of clock.
The K7N403601M and K7N401801M are implemented with
SAMSUNGs high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
LOGIC BLOCK DIAGRAM
A [0:16]or
A [0:17]
LBO
A0~A1
ADDRESS
REGISTER A2~A16 or A2~A17
BURST
ADDRESS
COUNTER
A0~A1
128Kx36 , 256Kx18
MEMORY
ARRAY
CLK
CKE
K
CS1
CS2
CS2
ADV
WE
BWx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
DATA-IN
K REGISTER
DATA-IN
K REGISTER
CONTROL
LOGIC
36 or 18
K OUTPUT
REGISTER
BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
- 2 - May 1999
Rev 3.0


Part Number K7N403601M
Description (K7N401801M / K7N403601M) 128Kx36 & 256Kx18 Pipelined NtRAM-TM
Maker Samsung semiconductor
Total Page 17 Pages
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