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Seiko Instruments Electronic Components Datasheet

S-8081B Datasheet

CR TIMER

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S-8081B pdf
Rev.1.1
CR TIMER
S-8081B
The S-8081B is a CMOS CR timer developed for appliances and
industrial equipment use. It consists of a CR oscillator, a 20-stage
divider, a power-on clear circuit, a trigger input chattering rejection
circuit, an internal voltage regulator, a level shift circuit, and an output
driver. It can be used as a high-precision, long-time monostable timer.
n Features
Wide power supply operating range : 4.5 to 16.5 V
Low current consumption : 200 µA max.(C = 200 k,
R = 0.0047 µF, open output )
Time can be set by external CR
Excellent oscillation stability because of built-in voltage regulator
Power-on clear circuit is integrated
Both trigger I/O inverting operation and set/reset operation can be
performed
n Applications
Time switch
Long time delay generator
n Pin Assignment
8-pin DIP/SOP
Top view
VSS 1
SET 2
OUT 3
RESET 4
S8081B
8 VDD
7 CR
6 DISCHARGE
5 TRIGGER
n Block Diagram
Figure 1
CR 7
DIS- 6
CHARGE
TRIGGER 5
SET 2
RESET 4
Oscil-
lation
circuit
20 - stage FF
FF20
tOUT
select
Control logic
Output
level shift
3 OUT
Input chattering
rejection circuit
Input
circuit
Input
circuit
Power ON
clear circuit
8 VDD
Voltage
regulator
1 VSS
Figure 2
Seiko Instruments Inc.
1


Seiko Instruments Electronic Components Datasheet

S-8081B Datasheet

CR TIMER

No Preview Available !

S-8081B pdf
CR TIMER
S-8081 B
n Timer Setting
The timer time tOUT is decided by an external resistor RT and an external capacitor CT.
tOUT=(K×RT×CT×219) sec.
K=time constant coefficient
10 stOUT10 hours (recommended)
RT50 k, CT100 pF (recommended)
Note : If other CT or RT is used than above recommended, the internal C and R influence tOUT and it becomes different
in each unit.
1 VSS
2 SET
3 OUT
VDD 8
CR 7
DISCH 6
CT**
RT*
4 RESET TRIG 5
CT : Connect between VDD and CR
RT : Connect between CR and DISCHARGE
* RT 50 k
** CT100PF
Figure 3 Connection of external CT and RT
TRIG-
GER
OUT
tOUT
tOUT
RESET
Figure 4 TRIGGER operation timing chart
SET
OUT
RESET
tOUT
tOUT
Figure 5 SET operation timing chart
tOUT=tOSC×219
tOSCK×RT×CT
(Recommended : RT50 k, CT100 pF)
n Operation
1. SET terminal
At the rise of SET terminal, OUT goes high (VDD) and frequency dividing operation starts.
This terminal has a pull-down resistor built in.
2. RESET terminal
By bringing RESET terminal high (VDD), OUT goes low (VSS) and the internal counter is reset.
Set or trigger input is ignored when reset is high.
This terminal has a pull-down resistor built in.
2 Seiko Instruments Inc.


Part Number S-8081B
Description CR TIMER
Maker Seiko Instruments Inc
Total Page 11 Pages
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