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Sirenza Microdevices
Sirenza Microdevices

SHF-0289Z Datasheet Preview

SHF-0289Z Datasheet

GaAs HFET

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SHF-0289Z pdf
SHF-0289
Product Description
SHF-0289Z Pb RoHS Compliant
& Green Package
Sirenza Microdevices’ SHF-0289 is a high performance AlGaAs/GaAs
Heterostructure FET (HFET) housed in a low-cost surface-mount plastic 0.05 - 6 GHz, 1.0 Watt
package. The HFET technology improves breakdown voltage while minimizing
GaAs HFETSchottky leakage current resulting in higher PAE and improved linearity.
Output power at 1dB compression for the SHF-0289 is +30dBm when
biased for Class AB operation at 7V,200mA. The +43 dBm third order
intercept makes it ideal for high dynamic range, high intercept point
requirements. It is well suited for use in both analog and digital wireless
communication infrastructure and subscriber equipment including 3G,
cellular, PCS, fixed wireless, and pager systems.
The matte tin finish on Sirenza’s lead-free package utilizes a post anneal-
ing process to mitigate tin whisker formation and is RoHS compliant per EU
Product Features
Directive 2002/95. This package is also manufactured with green molding • Now available in Lead Free, RoHS
compounds that contain no antimony trioxide nor halogenated fire retar- Compliant, & Green Packaging
dants.
• High Linearity Performance at 1.96 GHz
Typical Gain Performance (7V,200mA)
+30 dBm P1dB
40
35
30
25
20
15
Gmax
10
5 Gain
0
+43 dBm OIP3
+23.7 dBm IS-95 Channel Power
+14.6 dB Gain
• +21.7 dBm W-CDMA Channel Power
• High Drain Efficiency (>50% at P1dB)
• See App Note AN-032 for circuit details
Applications
0123456
Frequency (GHz)
• Analog and Digital Wireless Systems
• 3G, Cellular, PCS
• Fixed Wireless, Pager Systems
S y m b o l D e v ic e C h a ra c te ris tic s
T e s t C o n d itio n s , 2 5 C
V D S = 7 V , ID Q = 2 0 0 m A
(u n le s s o th e rw is e n o te d )
Te s t
F re q u e n c y
U n its
M in
Typ
M ax
Gm ax
M a x i m u m A v a i la b le G a i n
ZS= ZS*, Z L= ZL*
0 .9 0 G H z
1 .9 6 G H z
2 .1 4 G H z
dB
dB
dB
- 23 -
- 20 -
- 1 9 .5 -
S 21
G a in
In s e r ti o n G a i n [1 ]
P o w e r G a i n [2 ]
ZS= ZL= 5 0 O hm s
A p p lic a tio n C irc u it
0 .9 0 G H z
1 .9 6 G H z
dB
dB m
1 6 .7
1 3 .1
1 8 .5
1 4 .6
2 0 .3
1 6 .1
O IP 3
O u tp u t T h i r d O r d e r In te r c e p t P o i n t [2 ]
A p p lic a tio n C irc u it
1 .9 6 G H z
dB m
4 0 .5
4 3 .0
-
P 1dB
O u tp u t 1 d B C o m p r e s s i o n P o i n t [2 ]
A p p lic a tio n C irc u it
1 .9 6 G H z
dB m
2 8 .7
3 0 .2
-
P C HAN
NF
IS - 9 5 C h a n n e l P o w e r ( - 4 5 d B c A C P R )
N o i s e F i g u re [2 ]
A p p lic a tio n C irc u it
A p p lic a tio n C irc u it
1 .9 6 G H z
1 .9 6 G H z
dB m
dB
-
-
2 3 .7
4 .0
-
-
ID S S
gm
VP
B V GS
B V GD
R th
S a tu ra te d D ra in C u rre n t
Tra n c o n d u c ta n c e
P i n c h - O ff V o lta g e [1 ]
G a te - S o u r c e B r e a k d o w n V o lta g e [1 ]
G a te - D r a i n B r e a k d o w n V o lta g e [1 ]
T h e rm a l R e s is ta n c e
V DS= V DSP, V GS= 0 V
V D S = V D S P , V G S = -0 .2 5 V
V D S = 2 . 0 V , ID S = 1 . 2 m A
IG S = 2 . 4 m A , d r a i n o p e n
IG D = 2 . 4 m A , V G S = - 5 . 0 V
ju n c ti o n -to -le a d
mA
mS
V
V
V
oC /W
408
288
-3 .0
-
-
-
588
396
-1 .9
-1 7
-2 2
41
768
504
-1 .0
-1 5
-1 7
-
V DS
O p e r a ti n g V o lta g e [3 ]
d ra in-s o urc e
V-
- 8 .0
ID Q O p e r a t i n g C u r r e n t [3 ]
d ra in-s o urc e , q uie s c e nt
mA -
- 280
P D IS S
P o w e r D i s s i p a ti o n [3 ]
C-
- 1 .4
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board.
The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR.
[3] Maximum recommended power dissipation is specified to maintain TJ<140C at TL=85C. VDS * IDQ< 1.4W is recommended for continuous reliable operation.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent
rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or
systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MM
1
http://www.sirenza.com
EDS-101241 Rev E



Sirenza Microdevices
Sirenza Microdevices

SHF-0289Z Datasheet Preview

SHF-0289Z Datasheet

GaAs HFET

No Preview Available !

SHF-0289Z pdf
SHF-0289 1 Watt HFET
Absolute Maximum Ratings
MTTF is inversely proportional to the device junction
temperature. For junction temperature and MTTF
considerations the bias condition should also
satisfy the following expression:
PDC
< (T - T ) / R
JL
TH
where:
PDC = IDS * VDS (W)
T = Junction Temperature (°C)
J
TL = Lead Temperature (pin 4) (°C)
RTH = Thermal Resistance (°C/W)
MTTF @ TJ=150C exceeds 1E7 hours
Parameter
Symbol
Value
Unit
Drain Current
I 400 mA
DS
Forward Gate Current
I 2.4 mA
GSF
Reverse Gate Current
IGSR 2.4 mA
Drain-to-Source Voltage
V +9.0 V
DS
Gate-to-Source Voltage
VGS <-5 or >0 V
RF Input Power
PIN 400 mW
Operating Lead Temperature
TL
See Graph
°C
Storage Temperature Range
T
-40 to +165
°C
stor
Power Dissipation
PDISS
See Graph
W
Channel Temperature
TJ
+165
°C
Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation, the device
voltage and current must not exceed the maximum operating values
specified in the table on page 1.
Power Derating Curve
3.0
2.5
2.0
1.5
1.0
0.5 Operational (Tj<140C)
ABS MAX (Tj<165C)
0.0
-40 -10 20 50 80 110 140 170
Lead Temperature (C)
Design Considerations and Trade-offs
1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-to-
part precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is
recommended to maintain acceptable performance (RF and thermal).
2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB).
3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance.
Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished
using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each
device to eliminate the effects of pinchoff process variation.
4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage
should be increased to 8V to maximize P1dB. For small signal operation the OIP3 may be improved by reducing the
voltage and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V
bias condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipa-
tion limit (shown on page 1).
303 S. Technology Court , Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-101241 Rev E


Part Number SHF-0289Z
Description GaAs HFET
Maker Sirenza Microdevices
Total Page 4 Pages
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