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Sirenza Microdevices
Sirenza Microdevices

SLD-1000 Datasheet Preview

SLD-1000 Datasheet

4 Watt Discrete LDMOS FET

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SLD-1000 pdf
Product Description
Sirenza Microdevices’ SLD-1000 is a robust 4 Watt high performance
LDMOS transistor die, designed for operation from 10 to 2700MHz. It
is an excellent solution for applications requiring high linearity and effi-
ciency. The SLD-1000 is typically used as a driver or output stage for
power amplifier, or transmitter applications. These robust power tran-
sistors are fabricated using Sirenza’s high performance XEMOS IITM
process.
SLD-1000
4 Watt Discrete LDMOS FET -Bare Die
Functional Schematic Diagram
ESD
Protection
Product Features
4 Watt Output P1dB
Single Polarity Operation
19dB Gain at 900 MHz
XeMOS IITM LDMOS
Integrated ESD Protection, Class 1B
Aluminum Topside Metallization
Gold Backside Metallization
Gate
Manifold
Drain
Manifold
Source - Backside Contact
Applications
Base Station PA Driver
Repeaters
Military Communications
RFID
GSM, CDMA, Edge, WDCDMA
RF Specifications
Symbol
Parameter
Unit Min Typ Max
Frequency
Frequency of Operation
MHz
10
- 2700
Gain
3.5 Watts CW, 900 MHz
dB - 19 -
Efficiency
Linearity
RTH
Drain Efficiency at 3.5 Watts CW, 900 MHz
3rd Order IMD at 3.5 Watts PEP (Two Tone) 900 MHz
1dB Compression (P1dB) 900 MHz
Thermal Resistance (Junction-to-Case, mounted in package)
% - 43 -
dBc - -30 -
Watts
-
4
-
ºC/W
-
11
-
Test Conditions: Mounted in ceramic package and tested in SirenzaTEvaluation Board VDS = 28.0V, IDQ = 30mA, TMounting Surface = 25ºC
DC Specifications
Symbol
gm
VGS Threshold
VDS Breakdown
Ciss
Crss
Coss
RDSon
Parameter
Forward Transconductance @ 30mA IDS
IDS=3mA
1mA IDS Current
Input Capacitance (Gate to Source) VGS=0V, VDS=28V
Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V
Output Capacitance (Drain to Source) VGS=0V, VDS=28V
Drain to Source Resistance, VGS=10V VDS=250mV
Unit Min Typical Max
mA / V
150
Volts
3.0
4.2
5.0
Volts
65
70
pF 5.2
pF 0.2
pF 3.2
3.0 3.5
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1 EDS-104291 Rev C



Sirenza Microdevices
Sirenza Microdevices

SLD-1000 Datasheet Preview

SLD-1000 Datasheet

4 Watt Discrete LDMOS FET

No Preview Available !

SLD-1000 pdf
Quality Specifications
Parameter
Description
ESD Rating
Human Body Model
MTTF
200oC Channel
SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die
Unit
Volts
Hours
Typical
750
1.2 X 106
Contact Description
Pad #
Function
Description
1
Gate
Aluminum metallized manifold MOSFET Gate with ESD protection structure. (Topside contact)
2
Drain
Aluminum metallized manifold MOSFET Drain. (Topside contact)
3
Source
Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for
proper operation. (Backside contact)
Pad Diagram
ESD
Protection
Pad #1
Gate
Manifold
Pad #3
Backside Source = Ground
Pad #2
Drain
Manifold
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (VDS )
Gate Voltage (VGS), VDS =0
RF Input Power
35 Volts
20 Volts
+30 dBm
Load Impedance for Continuous Operation
Without Damage
10:1 VSWR
Output Device Channel Temperature
+200
ºC
Storage Temperature Range
-40 to +150
ºC
Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation see typical
setup values specified in the table on page one.
Note 1:
Gate voltage must be applied to to the device
concurrently or after application of drain voltage to
prevent potentially destructive oscillations. Bias voltages should
never be applied to the transistor unless it is properly termi-
nated on both input and output.
Note 2:
The required VGS corresponding to a specific IDQ will vary from
device to device due to the normal die-to-die variation in thresh-
old voltage with LDMOS transistors.
Note 3:
The threshold voltage (VGSTH) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature
Compensation.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-104291 Rev C


Part Number SLD-1000
Description 4 Watt Discrete LDMOS FET
Maker Sirenza Microdevices
Total Page 5 Pages
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