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TP5322 Datasheet Preview

TP5322 Datasheet

P-Channel Enhancement-Mode Vertical DMOS FET

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TP5322 pdf
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P-Channel Enhancement-Mode
Vertical DMOS FET
TPT5P3532222
Initial Release
Features
! Low threshold, -2.4V max.
! High input impedance
! Low input capacitance, 110pFmax.
! Fast switching speeds
! Low on resistance
! Free from secondary breakdown
! Low input and output leakage
! Complementary N- and P-channel devices
Application
! Logic level interfaces-ideal for TTL and CMOS
! Battery operated systems
! Photo voltaic devices
! Analog switches
! General purpose line drivers
! Telecom switches
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
BVDSS
BVDGS
±20V
Operating and Storage Temperature -55°C to +150°C
Soldering Temperature****
300°C
****Distance of 1.6mm from case for 10 seconds.
General Description
These low threshold enhancement-mode (normally-off)
transistors utilize an advanced vertical DMOS structure and
Supertex's well-proven silicon-gate manufacturing process. This
combination produces devices with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent in MOS
devices. Characteristic of all MOS structures, these devices are
free from thermal runaway and thermally-induced secondary
breakdown.
Supertex's vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very low
threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds are
desired.
Package Options
D
D
G
D
S
TO-243AA
(SOT-89)*
G
S
TO-236AB
(SOT-23)*
* "Green" Certified Package
Ordering Information
Order Number / Package
TO-243AA**
TO-236AB***
BVDSS /
BVDGS
RDS(ON)
(max)
TP5322N8
TP5322K1
-220V
12
TP5322N8-G* TP5322K1-G* -220V
12
**Same as SOT-89. Product supplied on 2000 piece carrier tape reels.
***Same as SOT-23. Products supplied on 3000 piece carrier tape reels.
VGS(th)
(max)
-2.4V
-2.4V
ID(ON)
(min)
-0.7A
-0.7A
Product Marking for SOT-89
TP3C
Where =2-week alpha date code
Product Marking for SOT-23
P3C
Where =2-week alpha date code
A042005
1 Rev. 3 September 14, 2004



Supertex
Supertex

TP5322 Datasheet Preview

TP5322 Datasheet

P-Channel Enhancement-Mode Vertical DMOS FET

No Preview Available !

TP5322 pdf
TP5322
Thwewrwm.DaatalShCeeht4aU.rcaomcteristics
Package ID (continuous) ID (pulsed)
Power Dissipation @
TA = 25°C
θJC
°C/W
TO-243AA
-0.26A
-0.90A
1.6W
15
TO-236AB
-0.12A
-0.70A
0.36W
200
*ID(continous) is limited by max rated Tj.
**Mounted on FR4 board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substate.
θJA
°C/W
78**
350
IDR*
-0.26A
-0.12A
IDRM
-0.9A
-0.7A
Electrical Characteristics (@25°C unless otherwise specified)
Symbol Parameter
Min Typ
BVDSS Drain-to-Source
Breakdown Voltage
-220
VGS(th)
VGS(th)
IGSS
IDSS
Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current
-1.0
Max
-2.4
4.5
-100
-10
-1.0
Units
V
V
mV/°C
nA
µA
mA
ID(ON)
RDS(ON)
On-State Drain Current
Static Drain-to-Source
ON-State Resistance
-0.7 -0.95
10
8.0
15
12
A
RDS(ON)
GFS
CISS
COSS
CRSS
td(ON)
tr
td(OFF)
tf
VSD
trr
Notes:
Change in RDS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time
1.7 %/°C
100 250
mmho
110
45 pF
20
10
15 ns
20
15
-1.8 V
300 ns
1) All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
2) All AC parameters sample tested.
Conditions
VGS = 0V, ID = -2mA
VGS = VDS, ID = -1mA
VGS = VDS, ID = -1mA
VGS = ±20V, VDS = 0V
VGS = 0V, VDS = Max Rating
VGS = 0V, VDS = 0.8 Max
Rating, TA = 125°C
VGS = -10V, VDS = -25V
VGS = -4.5V, ID = -100mA
VGS = -10V, ID = -200mA
VGS = -10V, ID = -200mA
VDS = -25V, ID = -200mA
VGS = 0V, VDS = -25V
f = 1MHz
VDD = -25V,
ID = -0.7A
RGEN = 25
VGS = 0V, ISD = -0.5A
VGS = 0V, ISD = -0.5A
Switching Waveforms and Test Circuit
0V
Input
-10V
0V
Output
t(ON)
td(ON)
tr
t(OFF)
td(OFF) tf
VDD
Pulse
Generator
RGEN
Input
D.U.T
OUT PUT
RL
VDD
Doc.# DSFP-TP5322
A042005
2
Rev. 3 September 14, 2004


Part Number TP5322
Description P-Channel Enhancement-Mode Vertical DMOS FET
Maker Supertex
Total Page 2 Pages
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