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Supertex  Inc
Supertex Inc

TN0106 Datasheet Preview

TN0106 Datasheet

N-Channel Enhancement-Mode Vertical DMOS FETs

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TN0106 pdf
Supertex inc.
TN0106
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold - 2.0V max.
High input impedance
Low input capacitance - 50pF typical
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
TN0106N3-G
TO-92
TN0106N3-G P002
TN0106N3-G P003
TN0106N3-G P005 TO-92
TN0106N3-G P013
TN0106N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Packing
1000/Bag
2000/Reel
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Value
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Typical Thermal Resistance
Package
θja
TO-92
132OC/W
Doc.# DSFP-TN0106
C080813
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
60V 3.0Ω
Pin Configuration
ID(ON)
(min)
2.0A
VGS(th)
(max)
2.0V
SOURCE
DRAIN
GATE
TO-92
Product Marking
SiTN YY = Year Sealed
0 1 0 6 WW = Week Sealed
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92
Supertex inc.
www.supertex.com



Supertex  Inc
Supertex Inc

TN0106 Datasheet Preview

TN0106 Datasheet

N-Channel Enhancement-Mode Vertical DMOS FETs

No Preview Available !

TN0106 pdf
TN0106
Thermal Characteristics
Package
(continIDuous)
TO-92
350mA
Notes:
† ID (continuous) is limited by max rated Tj .
ID
(pulsed)
2.0A
Power Dissipation
@TC = 25OC
1.0W
IDR
350mA
IDRM
2.0A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
60 - - V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage
0.6 - 2.0 V VGS = VDS, ID= 0.5mA
ΔVGS(th) Change in VGS(th) with temperature
- -3.2 -5.0 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero Gate voltage drain current
- - 10
VGS = 0V, VDS = Max Rating
-
-
500
µA VDS = 0.8 Max Rating,
VGS = 0V,TA = 125°C
ID(ON) On-state drain current
0.75 1.4
2.0 3.4
-
-
A VGS = 5.0V, VDS = 25V
VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance
- 2.0 4.5
- 1.6 3.0
Ω VGS = 4.5V, ID = 250mA
VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature
- 0.6 1.1 %/OC VGS = 10V, ID = 500mA
GFS Forward transductance
225 400
- mmho VDS = 25V, ID = 500mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 50 60
VGS = 0V,
- 25 35 pF VDS = 25V,
- 4.0 8.0
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- 2.0 5.0
-
-
-
3.0 5.0
6.0 7.0
3.0 6.0
VDD = 25V,
ns ID = 1.0A,
RGEN = 25Ω
VSD Diode forward voltage drop
1.0 1.5
V VGS = 0V, ISD = 500mA
trr Reverse recovery time
- 400 -
ns VGS = 0V, ISD = 500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
10%
t(ON)
90%
t(OFF)
td(ON)
tr
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Doc.# DSFP-TN0106
C080813
Supertex inc.
2 www.supertex.com


Part Number TN0106
Description N-Channel Enhancement-Mode Vertical DMOS FETs
Maker Supertex Inc
Total Page 5 Pages
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