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Supertex  Inc
Supertex Inc

TN0606 Datasheet Preview

TN0606 Datasheet

N-Channel Enhancement-Mode Vertical DMOS FETs

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TN0606 pdf
Supertex inc.
TN0606
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold - 2.0V max.
High input impedance
Low input capacitance - 100pF typical
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Product Summary
Part Number
TN0606N3-G
TN0606N3-G P002
Package Option
TO-92
Packing
1000/Bag
BVDSS/BVDGS
60V
RDS(ON)
(max)
1.5Ω
ID(ON)
(min)
3.0A
VGS(th)
(max)
3.0V
TN0606N3-G P003
TN0606N3-G P005 TO-92
2000/Reel Pin Configuration
TN0606N3-G P013
TN0606N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
SOURCE
DRAIN
Value
BVDSS
BVDGS
±20V
Product Marking
GATE
TO-92
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
SiTN YY = Year Sealed
0 6 0 6 WW = Week Sealed
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
Typical Thermal Resistance
TO-92
Package
TO-92
θja
132OC/W
Doc.# DSFP-TN0606
B080813
Supertex inc.
www.supertex.com



Supertex  Inc
Supertex Inc

TN0606 Datasheet Preview

TN0606 Datasheet

N-Channel Enhancement-Mode Vertical DMOS FETs

No Preview Available !

TN0606 pdf
TN0606
Thermal Characteristics
Package
(continIDuous)
TO-92
500mA
Notes:
† ID (continuous) is limited by max rated Tj .
ID
(pulsed)
3.2A
Power Dissipation
@TC = 25OC
1.0W
IDR
500mA
IDRM
3.2A
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source voltage
60 - - V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage
0.6 - 2.0 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- - -4.5 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage
- - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
1.2 2.0
3.0 6.7
-
-
A VGS = 5.0V, VDS = 25V
VGS = 10V, VDS = 25V
- - 15
VGS = 3.0V, ID = 250mA
RDS(ON) Static drain-to-source on-state resistance
- 1.5 2.0
Ω VGS = 5.0V, ID = 750mA
- 1.0 1.5
VGS = 10V, ID = 750mA
ΔRDS(ON) Change in RDS(ON) with temperature
- - 0.75 %/OC VGS = 10V, ID = 750mA
GFS Forward transductance
400 500
- mmho VDS = 25V, ID = 1.0A
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 100 150
VGS = 0V,
- 50 85 pF VDS = 25V,
- 10 35
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
--6
-
-
-
-
-
-
14
16
16
VDD = 25V,
ns ID = 1.5A,
RGEN = 25Ω
VSD Diode forward voltage drop
- 0.8 1.8
V VGS = 0V, ISD = 1.5A
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = 1.5A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
10%
t(ON)
td(ON)
tr
90%
t(OFF)
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Doc.# DSFP-TN0606
B080813
Supertex inc.
2 www.supertex.com


Part Number TN0606
Description N-Channel Enhancement-Mode Vertical DMOS FETs
Maker Supertex Inc
Total Page 5 Pages
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