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SEN01G64D1BF1SA-25R Datasheet Preview

SEN01G64D1BF1SA-25R Datasheet

SDRAM SO-DIMM

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SEN01G64D1BF1SA-25R pdf
Data Sheet
Rev.1.2 09.11.2010
1GB DDR2 SDRAM SO-DIMM
200 Pin SO-DIMM
SEN01G64D1BF1SA-30R
1GB PC2-6400 in FBGA Technology
RoHS compliant
Options:
Data Rate / Latency
DDR2 800 MT/s CL6
DDR2 667 MT/s CL5
Marking
-25
-30
Module density
1024MB with 8 dies and 1 rank
Standard Grade (TA)
(TC)
Grade E
(TA)
(TC)
Grade W
(TA)
(TC)
0°C to 70°C
0°C to 85°C
0°C to 85°C
0°C to 95°C
-40°C to 85°C
-40°C to 95°C
* The refresh rate has to be doubled when 85°C>TC>95°C
Environmental Requirements:
Operating temperature (ambient)
standard Grade
0°C to 70°C
Grade E
0°C to 85°C
Grade W
Operating Humidity
-40°C to 85°C
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
200-pin 64-bit Small Outline, Dual-In-Line Double
Data Rate Synchronous DRAM Module
Module organization: single rank 128M x 64
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
Serial Presence Detect with EEPROM
Gold-contact pad
This module is fully pin and functional compatible to
the JEDEC PC2-6400 spec. and JEDEC- Standard
MO-224. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component SAMSUNG
K4T1G084QF DIE Rev. F
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Eight internal device banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Figure: mechanical dimensions1
Swissbit AG
Industriestrasse 4
Ch-9552 Bronschhofen
1if no tolerances specified ± 0.15mm
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 14



Swissbit
Swissbit

SEN01G64D1BF1SA-25R Datasheet Preview

SEN01G64D1BF1SA-25R Datasheet

SDRAM SO-DIMM

No Preview Available !

SEN01G64D1BF1SA-25R pdf
Data Sheet
Rev.1.2 09.11.2010
This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the SO-DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization DDR2 SDRAMs used
128M x 64bit 8 x 128M x 8bit (1024Mbit)
Row
Addr.
14
Device Bank
Addr.
BA0, BA1,BA2
Column
Addr.
10
Refresh Module
Bank Select
8k S0#
Module Dimensions
in mm
67.60 (long) x 30 (high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
Module Density
SEN01G64D1BF1SA-25[E/W]R
1024 MB
SEN01G64D1BF1SA-30[E/W]R
1024 MB
Transfer Rate
6.4 GB/s
5.3 GB/s
Clock Cycle/Data bit rate
2.5ns/800MT/s
3.0ns/667MT/s
Latency
6-6-6
5-5-5
Pin Name
A0-9, A11 A13
A10/AP
BA0 BA2
DQ0 DQ63
DM0-DM7
DQS0 - DQS7
DQS0# - DQS7#
RAS#
CAS#
WE#
CKE0
CK0 CK1
Swissbit AG
Industriestrasse 4
Ch-9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Inputs, positive line
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 14


Part Number SEN01G64D1BF1SA-25R
Description SDRAM SO-DIMM
Maker Swissbit
Total Page 14 Pages
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