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SEP04G72G1AH2MT-xxR Datasheet Preview

SEP04G72G1AH2MT-xxR Datasheet

SDRAM registered DIMM

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SEP04G72G1AH2MT-xxR pdf
Data Sheet
Rev.1.2 14.02.2014
4GB DDR2 SDRAM registered DIMM
240 Pin RDIMM
SEP04G72G1AH2MT-xxR
4GByte in FBGA Technology
RoHS compliant
Options:
Data Rate / Latency
DDR2 667 MT/s CL5
DDR2 800 MT/s CL6
Marking
-30
-25
Module Density
4GByte with 36 dies and 2 ranks
Standard Grade (TC)
(TA)
0°C to 85°C
0°C to 70°C
Environmental Requirements:
Operating temperature (TC)
Standard Grade
Operating Humidity
0°C to 85°C
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
240-pin 72-bit Dual-In-Line Double Data Rate
Synchronous DRAM Module for server applications
Module organization: dual rank 512M x 64
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
Serial Presence Detect with EEPROM
Gold-contact pad
This module is fully pin and functional compatible to
the JEDEC PC2-6400 spec. and JEDEC- Standard
MO-237. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component MICRON
MT47H256M4CF-25 DIE-Revision H
256Mx4 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Eight internal device banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
mechanical dimensions
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 16



Swissbit
Swissbit

SEP04G72G1AH2MT-xxR Datasheet Preview

SEP04G72G1AH2MT-xxR Datasheet

SDRAM registered DIMM

No Preview Available !

SEP04G72G1AH2MT-xxR pdf
Data Sheet
Rev.1.2 14.02.2014
This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module (DIMM)
which is organized as x72 high speed CMOS memory arrays. The module uses internally configured quad-bank
DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR2
SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2
SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge
function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The
DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high
effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all
full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR2 SDRAMs used
36 x 256M x 4bit (1Gbit)
Row
Addr.
14
Device Bank
Select
BA0, BA1, BA2
Column
Addr.
11
Refresh
Module
Bank Select
8k S0#, S1#
Module Dimensions
in mm
133.33 (long) x 30(high) x 4 [max] (thickness)
Timing Parameters
Part Number
SEP04G72G1AH2MT-30R
SEP04G72G1AH2MT-25R
Module Density
4GByte
4GByte
Transfer Rate
5.3 GB/s
6.4 GB/s
Clock Cycle/Data bit
rate
3.0ns/667MT/s
2.5ns/800MT/s
Latency
5-5-5
6-6-6
Pin Name
A0 A13
BA0, BA1, BA2
DQ0 DQ63
CB0 CB7
DM0 DM8
RAS#
CAS#
WE#
CKE0 CKE1
CK0 CK1
CK0# CK1#
DQS0 DQS17
DQS0# DQS17#
S0# S1#
Address Inputs
Bank Address Inputs
Data Input / Output
Check Bits
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16


Part Number SEP04G72G1AH2MT-xxR
Description SDRAM registered DIMM
Maker Swissbit
Total Page 16 Pages
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