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Toshiba Electronic Components Datasheet

TC74VHC74FK Datasheet

DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR

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TC74VHC74FK pdf
TC74VHC74F/FN/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC74F,TC74VHC74FN,TC74VHC74FT,TC74VHC74FK
Dual D-Type Flip-Flop with Preset and Clear
The TC74VHC74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are
accomplished by setting the appropriate input low.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
High speed: fmax = 170 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 V to 5.5 V
Pin and function compatible with 74ALS74
Note: The JEDEC SOP (FN) is not available in
Japan.
TC74VHC74F
TC74VHC74FN
TC74VHC74FT
TC74VHC74FK
Weight
SOP14-P-300-1.27A
SOL14-P-150-1.27
TSSOP14-P-0044-0.65A
VSSOP14-P-0030-0.50
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2007-10-01


Toshiba Electronic Components Datasheet

TC74VHC74FK Datasheet

DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR

No Preview Available !

TC74VHC74FK pdf
Pin Assignment
TC74VHC74F/FN/FT/FK
IEC Logic Symbol
1CLR 1
1D 2
1CK 3
1PR 4
1Q 5
1Q 6
GND 7
CK D
QQ
CK D
QQ
(top view)
14 VCC
13 2CLR
12 2D
11 2CK
10 2PR
9 2Q
8 2Q
1PR
1CK
1D
1CLR
2PR
2CK
2D
2CLR
(4)
(3)
(2)
(1)
(10)
(11)
(12)
(13)
S
C1
1D
R
(5) 1Q
(6) 1Q
(9) 2Q
(8) 2Q
Truth Table
CLR
L
H
L
H
H
H
Inputs
PR D
HX
LX
LX
HL
HH
HX
X: Don’t care
Outputs
CK Q
Q
Function
XLH
Clear
XHL
Preset
XHH
LH
HL
Qn Qn No Change
Absolute Maximum Ratings (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC VCC/ground current
Power dissipation
Storage temperature
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
Tstg
0.5 to 7.0
0.5 to 7.0
0.5 to VCC + 0.5
20
±20
±25
±50
180
65 to 150
V
V
V
mA
mA
mA
mA
mW
°C
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
2 2007-10-01


Part Number TC74VHC74FK
Description DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR
Maker Toshiba
Total Page 10 Pages
PDF Download
TC74VHC74FK pdf
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