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Vitesse Semiconductor
Vitesse Semiconductor

VSC7139 Datasheet Preview

VSC7139 Datasheet

Quad Transceiver

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VSC7139 pdf
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7139
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Features
• Four Complete Transmitter/ Receiver Functions
in a Single Integrated Circuit
• Full Fibre Channel (T11) and Gigabit Ethernet
(IEEE 802.3z) Compliance
• 1.05Gb/s to 1.36Gb/s Operation per Channel
• Common or Per-Channel Transmit Byte Clocks
• TTL or PECL Reference Clock Input
• 1/10th or 1/20th Baud Rate Recovered Clocks
• Common and Per-Channel, Serial and Paral-
lel Loopback Controls
• Common Comma Detect Enable Inputs
• Per-Channel Comma Detect Outputs
• Cable Equalization in Receivers
• Automatic Lock-to-Reference
• 3.3V Power Supply, 2.67 W Max Power
Dissipation
• 208-Pin, 23mm BGA Packaging
General Description
The VSC7139 is a full-speed Quad Fibre Channel and Gigabit Ethernet Transceiver IC. Each of the four
transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters
and serializes the data onto high speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be
synchronous to the reference clock, a common transmit byte clock or a per-channel transmit byte clock. Each
receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters,
outputs a recovered clock and detects “Comma” characters. The VSC7139 contains on-chip (PLL) circuitry for
synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams.
VSC7139 Block Diagram (1 of 4 Channels)
Rx(0:9)
RCM
RCx1
RCx0
SYNCx
ENCDET
PLUP
SLPN
LPNx
Tx(0:9)
TBCx
REFT
REF+
REF-
RFCM
LTCN
10
QD
Serial to
Q Parallel D
QD
Comma
Detect
Loopback
4 Control
SEL
÷10/
÷20
÷10 Clock
Recovery
0
1
10
DQ
4
4
Clock
Multiply
Unit
x10/x20
Parallel
to Serial
DQ
0
1
Rx+
Rx-
Tx+
Tx-
RFCO0
RFCO1
G52196-0, Rev 3.3
5/14/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1



Vitesse Semiconductor
Vitesse Semiconductor

VSC7139 Datasheet Preview

VSC7139 Datasheet

Quad Transceiver

No Preview Available !

VSC7139 pdf
VITESSE
SEMICONDUCTOR CORPORATION
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Preliminary Datasheet
VSC7139
Functional Description
Notation
In this document, each of the four channels are identified as Channel A, B, C or D. When discussing a sig-
nal on any specific channel, the signal will have the Channel letter embedded in the name, i.e., TA(0:9).When
referring to the common behavior of a signal which is used on each of the four channels, a lower case xis
used in the signal name, i.e. Tx(0:9). Differential signals, i.e. RA+ and RA-, may be referred to as a single sig-
nal, i.e. RA, by dropping reference to the +and -. REFrefers to either the TTL input REFT, or the PECL
differential inputs REF+/REF-, whichever is used.
Clock Synthesizer
The VSC7139 clock synthesizer multiplies the reference frequency provided on the REF input by 10 or 20
to achieve a baud rate clock between 1.05GHz and 1.36GHz. The REF input can be either TTL or PECL. If
TTL, connect the TTL input clock to REFT. If PECL, connect the PECL inputs to REF+ and REF-. The internal
clock presented to the Clock Synthesizer is a logical XNOR of REFT and REF+/-. The reference clock will be
active HIGH if the unused input is HIGH. The reference clock is active LOW if the unused input is LOW. REFT
has an internal pull-up resistor. Internal biasing resistors set the proper DC level on REF+/- so AC-coupling may
be used.
The TTL outputs, RFCO0 and RFCO1, provide a clock that is frequency locked to the REF input. This
clock is derived from the clock synthesizer and is always 1/10 the baud rate, regardless of the state of the RFCM
input.
The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the
Loop Filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working
voltage rating and a good temperature coefficient, i.e., NPO is preferred but X7R may be acceptable. These
capacitors are used to minimize the impact of common mode noise on the Clock Multiplier Unit (CMU),
especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred
because if an X7R capacitor is used, the power supply noise sensitivity will vary with temperature.
For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor
between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,
C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor circuit,
a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.
Figure 1: Loop Filter Capacitors (Best Circuit)
CAP0
VSC7139
C1
CAP1
C2
C3
C1=C2=C3= >0.1µF
MultiLayer Ceramic
Surface Mount
NPO (Preferred) or X7R
5V Working Voltage Rating
Page 2
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52196-0, Rev 3.3
5/14/01


Part Number VSC7139
Description Quad Transceiver
Maker Vitesse Semiconductor
Total Page 18 Pages
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