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Vitesse Semiconductor
Vitesse Semiconductor

VSC8111 Datasheet Preview

VSC8111 Datasheet

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux

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VSC8111 pdf
Data Sheet
VSC8111
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Features
• Operates at Either STS-3/STM-1 (155.52 Mb/s) or
STS-12/STM-4 (622.08 Mb/s) Data Rates
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52 Mhz
or 622.08 Mhz High Speed Clock
• Dual 8 Bit Parallel TTL Interface
• Loss of Signal (LOS) Control
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Mode
• Meets Bellcore, ITU and ANSI Specifications for
Jitter Performance
• Single 3.3V Supply Voltage
• Low Power - 1.4 Watts Maximum
• SONET/SDH Frame Detection and Recovery
• 100 PQFP Package
General Description
The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication
unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high
speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-
ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.
VSC8111 Block Diagram
EQULOOP
LOSTTL
LOSPOL
LOS (Internal Signal)
RXDATAIN+/-
DQ
RXCLKIN+/-
0
1
FRAMER
OOF
FP
0 1:8
8
DEMUX
DQ
RXOUT[7:0]
1
0
Divide-by-8
1
RXLSCKOUT
TXDATAOUT+/-
TXCLKOUT+/-
FACLOOP
QD
1
0
1
0
10
8:1
MUX
8
QD
Divide-by-8
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
Divide-by-3/12
RX50MCK
LOOPTIM0
CMU
1
0
REFCLK
LOOPTIM1
LOS
EQULOOP
G52142-0, Rev 4.2
8/31/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1



Vitesse Semiconductor
Vitesse Semiconductor

VSC8111 Datasheet Preview

VSC8111 Datasheet

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux

No Preview Available !

VSC8111 pdf
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
Functional Description
The VSC8111 is designed to provide a SONET/SDH compliant interface between the high speed optical
networks and the lower speed User Network Interface (UNI) devices such as the PM5355 S/UNI-622 (or
PM5312 STTX). The VSC8111 transmit section converts 8 bit parallel data at 77.76 Mb/s or 19.44 Mb/s to a
serial bit stream at 622.08 Mb/s or 155.52 Mb/s, respectively. It also provides a Facility Loopback function
which loops the received high speed data and clock directly to the transmit outputs. A Clock Multiplier Unit
(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream
from input references frequency of 19.44, 38.88, 51.84 or 77.76 MHz. The CMU can be bypassed by using the
receive clock in loop timing mode thus synchronizing the entire part to a single clock (RXCLKIN).
The receive section provides the serial-to-parallel conversion, converting 155 Mb/s or 622 Mb/s to an 8 bit
parallel output at 19.44 Mb/s or 77.76 Mb/s, respectively. The receive section provides an Equipment Loopback
function which will loop the low speed transmit data and clock back through the receive section to the 8 bit par-
allel data bus and clock outputs. The receive section also contains a SONET/SDH frame detector circuit which
is used to provide frame recovery in the serial to parallel converter. The block diagram on page 1 shows the
major functional blocks associated with the VSC8111.
Transmit Section
Byte-wide data is presented to TXIN [7:0] and is clocked into the part on the rising edge of TXLSCKIN
(refer to Figure 1). The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins.
TXDATAOUT is clocked out on the falling edge of TXCLKOUT+. The serial output stream is synchronized to
the CMU generated clock which is a phase locked and frequency scaled version of the input reference clock.
External control inputs B0-B2 and STS12 select the multiply ratio of the CMU and either STS-3 (155 Mb/s) or
STS-12 (622 Mb/s) transmission (See Table 2). A divide-by-8 version of the CMU clock (TXLSCKOUT)
should be used to synchronize the transmit interface of the UNI device to the transmit input registers on the
VSC8111. (See Application Notes, Pg. 22)
Figure 1: Data and Clock Transmit Block Diagram
TXDATAOUT+
TXDATAOUT-
TXCLKOUT+
TXCLKOUT-
REFCLK
VSC8111
QD
QD
CMU
Divide-by-8
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
PM5355
QD
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98


Part Number VSC8111
Description ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux
Maker Vitesse Semiconductor
Total Page 26 Pages
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