STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
The VSC8115 contains an on-chip PLL consisting of a phase/frequency detector, a loop filter using one
external capacitor, a LC-based voltage-controlled oscillator (VCO), and a programmable frequency divider.
The phase/frequency detector compares the phase relationship between the VCO output and an external
19.44MHz LVTTL reference clock to make coarse adjustment to the VCO block so that its output is held within
+500ppm of the reference clock. The use of reference clock minimizes the PLL lock time during power up and
provides a stable output clock source in the absence of serial input data. The phase/frequency detector also com-
pares the phase relationship between the VCO output and the serial data input to make fine adjustment to the
VCO block. The loop filter converts the phase detector output into a smooth DC voltage. This DC voltage is
used as the input to the VCO block whose output frequency is a function of the input voltage. A programmable
frequency divider down converts the VCO output signal and provides two modes of operation: 622.08Mb/s
mode if STS12 is HIGH, or 155.52Mb/s mode if STS12 is LOW.
The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to
indicate that the PLL is locked to the serial data inputs and that valid data and clock are present at the high speed
differential outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or
the VCO has drifted away from the local reference clock by more than 500 ppm.
The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a
LVPECL input, and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate a loss
of signal condition and they are connected inside the part as shown in Figure 1. If either one of these two inputs
goes LOW and BYPASS is LOW, the VSC8115 will enter the loss of signal (LOS) state, and it will hold the
DATAOUT+/- output at logic LOW state. During the LOS state, the VSC8115 also will hold the output clock
CLKOUT+/- to within +500ppm of the REFCLK. See Table 1.
Most of the optical module has a signal detect output. This signal detect output indicates that there is suffi-
cient optical power, and it is typically active HIGH. If the signal detect output on the optical module is
LVPECL, it should be connected directly to the SD input on the VSC8115, and the LOCKREFN input needs to
be tied HIGH. If the signal detect output is LVTTL, it should be connected directly to the LOCKREFN input,
and the SD input needs to be tied HIGH.
The SD and LOCKREFN inputs also can be used for other applications when the users need to hold the
CLKOUT+/- output to within +500ppm of the reference clock and to force the DATAOUT+/- output to the
logic LOW state.
PLL Bypass Operation
The BYPASS pin is intended for use in production test, and it should be set at logic LOW in the normal
operation. If both BYPASS and MODE pins are set at logic HIGH, the VSC8115 will bypass the PLL and will
present an inverted version of the REFCLK to the clock output CLKOUT+/-. The REFCLK’s rising edge is
used to capture data at DATAIN+/- and transmit data at DATAOUT+/-. This bypass operation can be used to
facilitate the board debug process.
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52272-0, Rev. 1.1