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Vitesse Semiconductor
Vitesse Semiconductor

VSC8161 Datasheet Preview

VSC8161 Datasheet

2.488Gb/s SONET / SDH 16:1 Mux

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VSC8161 pdf
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8161
2.488Gb/s SONET / SDH
16:1 Mux with Clock Generator and Laser Driver
Features
• 16:1 Multiplexer Integrated with Clock
Multiplier and Laser Driver
• Monolithic Phase Locked Loop
• Laser Driver Provides up to 110 mA Current
• Differential 16-bit Parallel Data
• 100 pin 14x14 Plastic Quad Flat Package
• Jitter Generation Meets SONET OC-48 and
SDH STM-16 Requirements
• Companion to the VSC8162 1:16 Demulti-
plexer with Clock Recovery
• Supports Parity Checking at the 16-bit
Parallel Interface
General Description
The VSC8161 combines a Laser Driver and a clock multiplier with a 16:1 multiplexer to provide a single-
chip solution. The 16-bit data word is latched by an internal version of the reference clock, and is bit-multi-
plexed up to 2.488GHz. The on-chip PLL generates the internal 2.488GHz clock, which remains locked to the
155.52 MHz reference clock. The on-chip laser driver provides up to 60 mA modulation current and 50 mA bias
current.
VSC8161 Functional Block Diagram
D0+
D0-
D15+
D15-
PARITY+
PARITY-
CLK16+
CLK16-
REFCK+
REFCK-
Output
Retime
2.5GHz
PLL
Parity
Register
Divide
by 16
DINVERT
VIP
VIB
IOUT+
IOUT-
MIB
MIP
DINVALID+
DINVALID-
G52208-0, Rev.2.1
8/28/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1



Vitesse Semiconductor
Vitesse Semiconductor

VSC8161 Datasheet Preview

VSC8161 Datasheet

2.488Gb/s SONET / SDH 16:1 Mux

No Preview Available !

VSC8161 pdf
VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET / SDH
16:1 Mux with Clock Generator and Laser Driver
Advance Product Information
VSC8161
Functional Description
Multiplexer
The VSC8161 takes incoming 16-bit wide data at 155 MHz, D0 through D15, and converts it into a serial
data stream, with D0 transmitted first. CLK16 is the 155MHz low-speed clock output which is created by divid-
ing the internally generated 2.488 GHz clock by 16. The upstream device should use the CLK16 as its internal
reference and to register its low-speed data and parity output signals (See Fig 1). Care needs to be taken to meet
the data setup and hold timing on the parallel data.
Figure 1: VSC8161 Parallel Data Interface
In Out
CK
16
"upstream device"
D [0:15]
16
CLK16
In Out
CK
VSC8161
The timing relationship between the VSC8161 and the upstream device is described by the waveforms in
Fig. 5 and the associated parameters: tD, tDSU, and tDH appearing in Table 1.
The polarity of the serialized data can be inverted by the assertion of the DINVERT input. In either case,
however, the signal is retimed prior to the Laser Driver section of the VSC8161.
Clock Multiplier
The clock multiplier is fully integrated. No external components are needed. Jitter Generation of the clock
multiplier meets the requirement of Bellcore’s GR-253 (SONET) document. As in all of the frequency synthe-
sizers that employ a PLL, it is important to choose REFCK to be as jitter-free as possible.
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52208-0, Rev.2.1
8/28/98


Part Number VSC8161
Description 2.488Gb/s SONET / SDH 16:1 Mux
Maker Vitesse Semiconductor
Total Page 16 Pages
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