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Vitesse Semiconductor
Vitesse Semiconductor

VSC9187 Datasheet Preview

VSC9187 Datasheet

Telecomm / Datacomm

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VSC9187 pdf
TIMESTREAMTM PRODUCT FAMILY
VSC9187
VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric
Compliant with SONET Requirements as Stated in ANSI
T1.105 and Bellcore GR-253-CORE
Facilitates Hardware Based UPSR Switching in
Accordance with Telcordia GR-1400-CORE
Thermally Enhanced 360 CCGA Package
IEEE P1149.1 Test Access Port
FEATURES:
3024x3024 (5 G) Non-Blocking VT1.5 TSI, 6048x6048 (10 Gb/s)
VT1.5 TSI with 2:1 UPSR Input Pre-selection
2x9x622 Mb/s STS-12 LVDS Backplane Inputs with Integrated
Retiming and Alignment
Working and Protection 2 x 9 x 622 Mb/s STS-12 LVDS Outputs
Supports 2:1 Hardware VT1.5 UPSR Selection when used in
Conjunction with VSC9188 VT1.5 Pointer Processor and
Column Aligner
6 Service & 6 Protection STS-1 like Serial 51.84 Mb/s
Interfaces for Local Drop Interfaces
Integrated STS-1 Frame Delay Management on Output for
use in Subtended STS-1 Switch Fabrics
SPECIFICATIONS:
2.5/1.8V Power Supply; 0.18um Technology
APPLICATIONS:
VT1.5 Time Slot Interchange (TSI)
BENEFITS:
Low cost, low power, VT1.5 switching
KEY SPECIFICATIONS:
PARAMETERS
Vdd_core
Vdd_IO
DESCRIPTION
Voltage for Core
Voltage of IO cells
POWER DISSIPATION
IDD_2.5
IDD_1.8
PD_typical
PD_peak
Peak power supply current from 2.5V VDD
Peak power supply current from 1.8V VDD
Typical power dissipation
Peak power dissipation
Data STS-12 Inputs I/O
Service Data STS-1 Inputs I/O
STS1 Reference Clock Input
622Mb/s LVDS
51.84Mb/s LVDS
51.84MHz LVDS
Min
1.65V
2.3V
51.83MHz
Max
1.95V
2.7V
Conditions
Recommended 1.8V
Recommended 2.5V
0.4 A
2.25 A
4W
5W
51.85MHz
Nominal
Nominal
Nominal
PB-VSC9187-001



Vitesse Semiconductor
Vitesse Semiconductor

VSC9187 Datasheet Preview

VSC9187 Datasheet

Telecomm / Datacomm

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VSC9187 pdf
VSC9187
VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric
GENERAL DESCRIPTION:
The VSC9187 is a VT1.5 Time Slot
Interchange (TSI) Device. It provides a
fully non blocking cross connect for 3024
VT1.5's that are all frequency, phase and
column aligned in addition to a pre-
grooming 2:1 UPSR selection. The device receives 9 x 622
Mb/s STS-12 working and protection backplane inputs and
performs all necessary functions to retime and align these
signals from the backplane. VT1.5 tributaries are then pre-
selected with a hardware 2:1 UPSR switch from the working
and protection timeslot with programmable holdover and pre-
hold switch timers. The results of the 2:1 hardware selection
are then made available to an internal 3024x3024 VT1.5 non-
blocking grooming switch, allowing a 5G UPSR ring to be
terminated. Alternatively, the 9 protection STS-12 backplane
inputs can remain unused and the VSC9188 can act as a 5G
VT1.5 switch. Output STS-1 delay management following the
crossconnect allows the VSC9187 to be used in subtended
switch applications with large scale STS-1 crossconnects
such as the VSC9182 40Gb/s STS-1 TSI.
VSC9187 BLOCK DIAGRAM:
LEG_DI_S[5:0]
LEG_RCLK_S
LEG_RSYN_S
STS_DI_[8:0]
TDM
MUX
[8] MUX
9 x 622Mb/s
STS-12
Serial
Backplane
Inputs
(Service)
[7:0]
[8:0]
LASB
LEG_DI_P[5:0]
LEG_RCLK_P
LEG_RSYN_P
STS_DI_[17:9]
TDM
MUX
Low-Order Alarm Status Byte (LASB)
Inserted by VSC9188
(contains VTI.5 PM summary)
[17] MUX
9 x 622Mb/s
STS-12
Serial
Backplane
Inputs
(Protection)
[16:9]
[17:9]
LASB
HS-CLK LS-CLK SYNC M-SYNC
JTAG Interface
System Interface and PLL
TDM
DEMUX
LEG_DO_S[5:0]
LEG_TCLK_S
LEG_TSYN_S
[8:0]
9 x 622Mb/s
STS-12
Serial
Backplane
Inputs
(Service)
STS_DO_[8:0]
TDM
DEMUX
LEG_DO_P[5:0]
LEG_TCLK_P
LEG_TSYN_P
[8:0]
9 x 622Mb/s
STS-12
Serial
Backplane
Outputs
(Protection)
STS_DO_[17:9]
CPU Interface
Your Partner for Success.
For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or sales@vitesse.com
©2002 Vitesse Semiconductor Corporation
741 Calle Plano
Camarillo, CA 93012, USA
Tel: +1 805.388.3700
Fax: +1 805.987.5896
www.vitesse.com


Part Number VSC9187
Description Telecomm / Datacomm
Maker Vitesse Semiconductor
Total Page 2 Pages
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