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XC3S250E Datasheet

(XC3Sxx00E) Spartan-3E FPGA Family

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R Spartan-3E FPGA Family:
Complete Data Sheet
DS312 March 21, 2005
00
Module 1:
Introduction and Ordering Information
DS312-1 (v1.1) March 21, 2005
6 pages
• Introduction
• Features
• Architectural Overview
• Package Marking
Ordering Information
Module 2:
Functional Description
DS312-2 (v1.1) March 21, 2005
96 pages
• Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
Configuration
• Powering Spartan-3E FPGAs
Module 3:
DC and Switching Characteristics
DS312-3 (v1.0) March 1, 2005
18 pages
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
• Switching Characteristics
- DCM Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312-4 (v1.1) March 21, 2005
72 pages
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
IMPORTANT NOTE: The Spartan-3E FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
navigation in this volume.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 March 21, 2005
www.xilinx.com
1



Xilinx
Xilinx

XC3S250E Datasheet Preview

XC3S250E Datasheet

(XC3Sxx00E) Spartan-3E FPGA Family

No Preview Available !

XC3S250E pdf
R
DS312-1 (v1.1) March 21, 2005
06 Spartan-3E FPGA Family:
Introduction and Ordering
Information
0 0 Advance Product Specification
Introduction
The Spartan™-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic applica-
tions. The five-member family offers densities ranging from
100,000 to 1.6 million system gates, as shown in Table 1.
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of config-
uration. These Spartan-3E enhancements, combined with
advanced 90 nm process technology, deliver more function-
ality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection, and digital television equipment.
The Spartan-3E family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
• Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
- True LVDS, RSDS, mini-LVDS differential I/O
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- Enhanced Double Data Rate (DDR) support
• Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks and eight clocks for each half of
device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
- Low-cost Xilinx Platform Flash with JTAG
• Complete Xilinx ISE™, WebPACK™ development
system support
• MicroBlaze™, PicoBlazeembedded processor cores
• Fully compliant 32-/64-bit 33/66 MHz PCI support
• Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
- Pb-free packaging options
Table 1: Summary of Spartan-3E FPGA Attributes
Device
System
Gates
Equivalent
Logic
Cells
CLB Array
(One CLB = Four Slices)
Total Total
Rows Columns CLBs Slices
XC3S100E 100K
2,160
22
16
240 960
XC3S250E 250K
5,508
34
26
612 2,448
XC3S500E 500K 10,476
46
34 1,164 4,656
XC3S1200E 1200K 19,512
60
46 2,168 8,672
XC3S1600E 1600K 33,192
76
58 3,688 14,752
Distributed
RAM bits(1)
15K
38K
73K
136K
231K
Block
RAM
bits(1)
72K
216K
360K
504K
648K
Maximum
Dedicated
Maximum Differential
Multipliers DCMs User I/O I/O Pairs
4 2 108 40
12 4 172
68
20 4 232
92
28 8 304
124
36 8 376
156
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-1 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
1


Part Number XC3S250E
Description (XC3Sxx00E) Spartan-3E FPGA Family
Maker Xilinx
Total Page 30 Pages
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