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Xilinx  Inc
Xilinx Inc

X1725665DD8M Datasheet Preview

X1725665DD8M Datasheet

QPRO Family of XC1700D QML Configuration PROMs

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X1725665DD8M pdf
0
R QPRO Family of XC1700D QML
Configuration PROMs
DS070 (v2.1) June 1, 2000
02
Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing.)
• Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617.
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS EPROM process
• Available in 5V version only
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
Product Specification
Description
The XC1700D QPRO™ family of configuration PROMs pro-
vide an easy-to-use, cost-effective method for storing Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS070 (v2.1) June 1, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1



Xilinx  Inc
Xilinx Inc

X1725665DD8M Datasheet Preview

X1725665DD8M Datasheet

QPRO Family of XC1700D QML Configuration PROMs

No Preview Available !

X1725665DD8M pdf
QPRO Family of XC1700D QML Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can
be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid
confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices.
When RESET is active, the address counter is held at zero,
and the DATA output is put in a high-impedance state. The
polarity of this input is programmable. The default is active
High RESET, but the preferred option is active Low RESET,
because it can be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 programmer software. Third-party programmers
have different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into low-ICC
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
VPP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
R
ation, this pin must be connected to VCC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
VPP floating!
VCC and GND
VCC is positive supply pin and GND is ground pin.
PROM Pinouts
Pin Name
DATA
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
VPP
VCC
8-pin
1
2
3
4
5
6
7
8
Capacity
Device
XC1736D
XC1765D
XC17128D
XC17256D
Configuration Bits
36,288
65,536
131,072
262,144
Number of Configuration Bits, Including
Header for Xilinx FPGAs and Compatible
PROMs
Device
XC3000/A series
XC4000 series
XQ4005E
XQ4010E
XQ4013E
Configuration Bits
14,819 to 94,984
95,008 to 247,968
95,008
178,144
247,968
PROM
XC1765D to
XC17128D
XC17128D to
XC17256D
XC17128D
XC17256D
XC17256D
2
www.xilinx.com
DS070 (v2.1) June 1, 2000
1-800-255-7778
Product Specification


Part Number X1725665DD8M
Description QPRO Family of XC1700D QML Configuration PROMs
Maker Xilinx Inc
Total Page 10 Pages
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