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Zarlink Semiconductor
Zarlink Semiconductor

ZL50052 Datasheet Preview

ZL50052 Datasheet

8 K Channel Digital Switch

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ZL50052 pdf
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Features
• 8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 16 input
streams and 16 output streams
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
• Backplane port accepts 8 input and 8 output ST-
BUS streams with data rate of 32.768 Mbps
• Local port accepts 8 input and 8 output ST-BUS
streams with data rate of 32.768 Mbps
• Exceptional input clock jitter tolerance (14 ns)
• Per-stream bit delay for Local and Backplane
input streams
• Per-stream advancement for Local and
Backplane output streams
ZL50052
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (32 Mbps),
and 16 Inputs and 16 Outputs
Data Sheet
December 2003
Ordering Information
ZL50052GAC 196 ball PBGA
-40°C to +85°C
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
• Per-channel message mode for Local and
Backplane output streams
• Connection memory block programming for fast
device initialization
• Automatic selection between ST-BUS and GCI-
Bus operation
• Non-multiplexed Motorola microprocessor
interface
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-7
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-7
BSTo0-7
Backplane
Interface
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-7
BORS
FP8i
C8i
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50052 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.



Zarlink Semiconductor
Zarlink Semiconductor

ZL50052 Datasheet Preview

ZL50052 Datasheet

8 K Channel Digital Switch

No Preview Available !

ZL50052 pdf
ZL50052
• Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
• Memory Built-In-Self-Test (BIST), controlled via microprocessor register
• 1.8 V core supply voltage
• 3.3 V I/O supply voltage
• 5 V tolerant inputs, outputs and I/Os
Applications
• Central Office Switches (Class 5)
• Media Gateways
• Class-Independent Switches
• Access Concentrators
• Scalable TDM-Based Architectures
• Digital Loop Carriers
Data Sheet
2
Zarlink Semiconductor Inc.


Part Number ZL50052
Description 8 K Channel Digital Switch
Maker Zarlink Semiconductor
Total Page 30 Pages
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