8Gb NAND Flash

HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash www.DataSheet4U.com 8Gb NAND FLASH HY27UG088G5M HY27UG088GDM This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Dec. 2006 1 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash Document Title 8Gbit (1Gx8bit) NAND Flash Memory Revision History Revision No. www.DataSheet4U.com History Initial Draft. 1) Add HY27UG088G5M & HY27UG088GDM Products. - Texts & figures are added. 2) Change Ac Characteristics tR Before After 20 25 tCLS tAR 10 15 tWP 12 15 tDS 12 15 tREA 18 20 tWC 25 30 tRHZ 30 50 tADL 70 100 tCHZ 30 50 tRP 12 15 tCEA 25 35 tRC 25 30 Draft Date Sep. 08. 2005 Remark Initial 0.0 0.1 Before After 12 15 Oct. 23. 2005 Preliminary 3) Add tCRRH (100ns, Min) - tCRRH: cache Read RE High 4) Change 3rd Read ID - 3rd Read ID is changed to C1h - 3rd Byte of Device Identifier Table is added. 5) Change NOP - Number of Partial Program Cycle in the same page is changed to 4. 6) Delete Concurrent Operation. 1) Change AC Characteristics tREA 0.2 Before After 20 25 tCEA 35 30 tCS 20 25 Nov. 16. 2005 Preliminary Rev. 0.6 / Dec. 2006 2 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash Revision History Revision No. 1) Correct Read ID naming 2) Add ECC algorithm. (1bit/512bytes) 3) Change valid block number (max) www.DataSheet4U.com - Continued History Draft Date Remark valid block number Before After 8092 8192 Jun. 20. 2006 ICC2 Typ 25 15 Max 45 30 ICC3 Typ 25 15 Max 45 30 Preliminary 0.3 4) Change NOP 5) Change DC characterics ICC1 Typ Before After 25 15 Max 45 30 6) Delete TSOP 1CE package dimension & figures. 0.4 0.5 0.6 1) Delete Preliminary. 1) Correct copy back function. 1) Delete PRE function. 2) Delete Lock & Unlock function. 3) Delete Auto Read function. Jul. 10. 2006 Oct. 02. 2006 Dec. 26. 2006 Rev. 0.6 / Dec. 2006 3 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 width. - Multiplexed Address/ Data www.DataSheet4U.com - Pinout compatibility for all densities STATUS REGISTER ELECTRONIC SIGNATURE - 1st cycle: Manufacturer Code - 2nd cycle: Device Code CHIP ENABLE DON'T CARE - Simple interface with microcontroller SERIAL NUMBER OPTION HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles (with 1bit/512byte ECC) - 10 years Data Retention PACKAGE - HY27UG088G5M-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27UG088G5M-T (Lead) - HY27UG088G5M-TP (Lead Free) - HY27UG088GDM-UP :52- ULGA (12 x 17 x 0.65 mm) - HY27UG088GDM-DP (Lead Free) SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to 3.6V : HY27UG088G(5/D)M Memory Cell Array = (2K+ 64) Bytes x 64 Pages x 8,192 Blocks PAGE SIZE - x8 device : (2K + 64 spare) Bytes : HY27UG088G(5/D)M BLOCK SIZE - x8 device: (128K + 4K spare) Bytes PAGE READ / PROGRAM - Random access: 25us (max.) - Sequential access: 30ns (min.) - Page program time: 200us (typ.) COPY BACK PROGRAM MODE - Fast page copy without external buffering CACHE PROGRAM MODE - Internal Cache Register to improve the program throughput FAST BLOCK ERASE - Block erase time: 2ms (Typ.) Rev. 0.6 / Dec. 2006 4 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 1. SUMMARY DESCRIPTION The HYNIX HY27UG088G(5/D)M series is a 1Gx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 8192 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. www.DataSheet4U.com A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block. Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modifying can be locked using the WP input pin. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27UG088G(2/5/D)M extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out. This device includes also extra features like OTP/Unique ID area, Read ID2 extension. The HYNIX HY27UG088G(5/D)M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm. 1.1 Product List PART NUMBER HY27UG088G5M HY27UG088GDM ORIZATION x8 x8 VCC RANGE 2.7V - 3.6 Volt 2.7V - 3.6 Volt PACKAGE 48TSOP1 52-ULGA Rev. 0.6 / Dec. 2006 5 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash www.DataSheet4U.com Figure1: Logic Diagram IO7 - IO0 CLE ALE CE RE WE WP R/B Vcc Vss NC Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection Table 1: Signal Names Rev. 0.6 / Dec. 2006 6 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash www.DataSheet4U.com Figure 2. 48TSOP1 Contactions, x8 Device (2CE) Rev. 0.6 / Dec. 2006 7 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash www.DataSheet4U.com Figure 3. 52-ULGA Contactions, x8 Device, Dual interface (Top view through package) Rev. 0.6 / Dec. 2006 8 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash 1.2 PIN DESCRIPTION Pin Name IO0-IO7 Description DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CHIP ENABLE This input controls the selection of the device. When the device is busy CE1, CE2 low does not deselect the memory. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The VCC supplies the power for all the operations (Read, Write, Erase). GROUND NO CONNECTION www.DataSheet4U.comCLE ALE CE1, CE2 WE RE WP R/B1, R/B2 VCC VSS NC Table 2: Pin Description NOTE: 1. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Rev. 0.6 / Dec. 2006 9 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0 A8 A12 A20 A28 IO1 A1 A9 A13 A21 A29 IO2 A2 A10 A14 A22 L (1) IO3 A3 A11 A15 A23 L (1) IO4 A4 L(1) A16 A24 L (1) IO5 A5 L(1) A17 A25 L (1) IO6 A6 L(1) A18 A26 L (1) IO7 A7 L(1) A19 A27 L(1) www.DataSheet4U.com Table 3: Address Cycle Map(2CE & Dual) NOTE: 1. L must be set to Low. Acceptable command during busy FUNCTION READ 1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM (start) COPY BACK PGM (start) CACHE PROGRAM BLOCK ERASE READ STATUS REGISTER RANDOM DATA INPUT RANDOM DATA OUTPUT CACHE READ START CACHE READ EXIT 1st CYCLE 00h 00h 90h FFh 80h 85h 80h 60h 70h 85h 05h 00h 34h 2nd CYCLE 30h 35h 10h 10h 15h D0h E0h 31h - 3rd CYCLE - Yes Yes Table 4: Command Set Rev. 0.6 / Dec. 2006 10 HY27UG088G(5/D)M Series 8Gbit (1Gx8bit) NAND Flash CLE H L H L www.DataSheet4U.com ALE L H L H L L L X X X X CE L L L L L L(1) L X X X H WE Rising Rising Rising Rising Rising H H X X X X RE H H H H H Falling H X X X X WP X X H H H X X H H L 0V/Vcc Read Mode MODE Command Input Address Input(5 cycles) Co