MC80F7708
description in “Figure12-10 / Figure 12-11/Figure 12-15 8bit/16bit capture mode”.
VERSION 1.1 (February 2, 2009)
Modify BIRR description in “Figure24-1 Block Diagram of BIR (Built-In Reset)”. Modify Port structures(R43, R42 ,R20/AN0~R23/AN3, R24/AN4~R25/AN5)
VERSION 1.0 (April 1, 2008)
Corrected PSW(NVGBHIZC) for “INC A” instruction from N-----ZC to N-----Z- at " Arithmetic / Logic Operation" on page iv.
VERSION 0.7 (OCT 17, 2007)
Modify CTR(Contrast Controller Level Selection ) in Figure 18-3 LCD Bias Control
VERSION 0.6 (MAY 02, 2007)
Modify FLASH memory endurance : 1000 cycles to 100 cycles (page 1).
VERSION 0.5 (APR 09, 2007)
Remove P-MOS protection diode of LCD SEG or pin(R50~R57, R60~R67, R70~ R77) in page 13. Add R7, R4, R4IO, R4OD and R4PU registers to “Table 8-1 Control Registers”. (page 27, 28) Fix reset value of R4OD and R4PUfrom 00-0--0-B to -000000-B and 0000000-B. (page 37) Change R6IO(0CDh) to R7IO(0B4h) and add R74 ~ R75 in R7 port decribing Figure(page...
