S2043 Datasheet | AMCC

DESCRIPTION S2042/S2043 S2042/S2043 FEATURES - Functionally pliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards - S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference - S2043 receiver PLL configured for clock and data recovery - 1062, 531 and 266 Mb/s operation - 10- or 20-bit parallel TTL patible interface - 1 watt typical power dissipation for chipset - +3.3/+5V power supply - Low-jitter serial PECL patible interface - Lock detect - Local loopback - 10mm x 10mm 52 PQFP package - Fibre Channel framing performed by receiver - Continuous downstream clocking from receiver - TTL patible outputs possible with +5V I/O power supply The S2042 and S2043 transmitter and receiver pair are designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chipset is selectable to 1062, 531 or 266 Mbit/s data rates with associated 10- or 20-bit data word. The chipset performs parallel-to-serial and serial-toparallel conversion and framing for block-encoded data. The S2042 on-chip PLL synthesizes the highspeed clock from a low-speed reference. The S2043 on-chip PLL synchronizes directly to ining digital signals to receive the data stream. The transmitter and receiver each support differential PECL-patible I/O for fiber optic ponent interfaces, to minimize crosstalk and maximize data integrity. Local loopback allows for system diagnostics. The TTL I/O section can operate from either a +3.3V or a +5V power supply. With a 3.3V power supply the chipset dissipates only 1W typically. Figure 1 shows a typical network configuration incorporating the chipset. The chipset is patible with AMCC’s S2036 Open Fiber Control (OFC) device. APPLICATIONS High-speed data munications - Superputer/Mainframe - Workstation - Switched networks - Proprietary extended backplanes - Mass storage...