* Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards
* S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference
* S2043 receiver PLL configured for clock and data recovery
S2043
AMCC
211.04 KB
(s2042 / s2043) high performance serial interface circuits.
www.DataSheet4U.com PRELIMINARY DEVICE SPECIFICATION ® HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK SERIAL GENERATOR HIGH PERFORMANC.
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