Description
at any time without notice.
No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication.
Features
- 2 Process Technology 4 Super7™ Platform Initiative 4 AMD-K6™-2E Processor Microarchitecture Overview 7 Cache, Instruction Prefetch, and Predecode Bits 12 Instruction Fetch and Decode 13 Centralized Scheduler 17 Execution Units 18 Branch-Prediction Logic 20 Registers 23 Model-Specific Registers (MSR) 40 Memory Management Registers 47 Paging 49 Descriptors and Gates 52 Exceptions and Interrupts 55 Instructions Supported by the AMD-K6™-2E Processor 56
2
Internal Architecture 7
2.1 2.2.