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DF011 - CMOS Gate Array

General Description

DF011 is a static, master-slave D flip-flop.

RESET is asynchronous and active low.

Output is unbuffered and changes state on the rising edge of the clock.

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Datasheet Details

Part number DF011
Manufacturer AMI
File Size 31.77 KB
Description CMOS Gate Array
Datasheet download datasheet DF011 Datasheet

Full PDF Text Transcription for DF011 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DF011. For precise diagrams, and layout, please refer to the original PDF.

Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD Description DF011 is a static, master-slave D flip-flop. RESET is asynchronous and active low. Output is unbuffered an...

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ip-flop. RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table Pin Loading DF011 DQ C R RN D C Q LXXL HL ↑L HH ↑H H X L NC NC = No Change Equivalent Load D 1.0 C 1.0 RN 1.0 Equivalent Gates ................ 8.0 HDL Syntax Verilog .................... DF011 inst_name (Q, C, D, RN); VHDL...................... inst_name: DF011 port map (Q, C, D, RN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 17.8 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.

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