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DF021 - CMOS Gate Array

General Description

DF021 is a static, master-slave D flip-flop.

SET is asynchronous and active low.

Output is unbuffered and changes state on the rising edge of the clock.

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Datasheet Details

Part number DF021
Manufacturer AMI
File Size 30.68 KB
Description CMOS Gate Array
Datasheet download datasheet DF021 Datasheet

Full PDF Text Transcription for DF021 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DF021. For precise diagrams, and layout, please refer to the original PDF.

Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD Description DF021 is a static, master-slave D flip-flop. SET is asynchronous and active low. Output is unbuffered and ...

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ip-flop. SET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table Pin Loading DF021 DSQ C SN D C Q L XXH HL ↑L HH ↑H H X L NC NC = No Change Equivalent Load D 1.0 C 1.0 SN 2.1 Equivalent Gates ................... 7.0 HDL Syntax Verilog...................DF021 inst_name (Q, C, D, SN); VHDL...................... inst_name: DF021 port map (Q, C, D, SN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 14.5 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.

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