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AMI

DF211 Datasheet Preview

DF211 Datasheet

CMOS Gate Array

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')
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
DF211 is a static, master-slave, multiplexed scan D flip-flop. RESET is asynchronous and active low. Output is
unbuffered and changes state on the rising edge of the clock.
Logic Symbol
DF211
D
C
SD
SE R
Q
Truth Table
C
X
L
D RN SD SE Q
HHX L
L HX L
XHHH
XHLH
XLXX
XHXX
NC = No Change
H
L
H
L
L
NC
Pin Loading
Equiva-
lent
Load
C 1.0
D 1.0
RN 1.0
SD 1.0
SE 2.1
Equivalent Gates ................ 11.0
HDL Syntax
Verilog .................... DF211 inst_name (Q, C, D, RN, SD, SE);
VHDL...................... inst_name: DF211 port map (Q, C, D, RN, SD, SE);
Size And Power Characteristics
Parameter
Static IDD (TJ = 85°C)
EQLpd
See page 2-15 for power equation.
Value
TBD
22.3
Units
nA
Eq-load
Propagation Delays
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
From Delay (ns) To Parameter
1
Number of Equivalent Loads
258
C
Q
tPLH
tPHL
0.74
0.58
0.79
0.63
RN
Q tPHL
0.32
0.36
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
0.94
0.74
0.46
1.10
0.82
0.55
10 (max)
1.21
0.87
0.60
3-73




AMI

DF211 Datasheet Preview

DF211 Datasheet

CMOS Gate Array

No Preview Available !

')
$0,+*  PLFURQ &026 *DWH $UUD\
Timing Constraints
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To
Parameter
Value
Min C Width
Min C Width
Min RN Width
Min D Setup
Min D Hold
Min SD Setup
Min SD Hold
Min SE Setup
Min SE Hold
Min RN Setup
Min RN Hold
High
Low
Low
tw
tw
tw
tsu
th
tsu
th
tsu
th
tsu
th
0.74
0.85
0.53
0.69
0.17
0.69
0.17
0.84
0.17
0.37
0.33
Logic Schematic
RN
R
D
SEN
SE
SD
CB
R
CN
CN
SE SEN
CB
C CB
CN
3-74
®
CN
R
CB
CB
CN
Q


Part Number DF211
Description CMOS Gate Array
Maker AMI
Total Page 2 Pages
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