DF411 - CMOS Gate Array

Description

DF41x is a family of static, master-slave, multiplexed scan D flip-flops.

RESET is asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

AMI

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Datasheet Details

Part number	DF411
Manufacturer	AMI
File Size	46.34 KB
Description	CMOS Gate Array
Datasheet	DF411 Datasheet
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')[ ® $0,+* PLFURQ &026 *DWH $UUD Description DF41x is a family of static, master-slave, multiplexed scan D flip-flops. RESET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF41x D C SD SE R Q Q Truth Table C D RN SD SE Q QN ↑HHX LHL ↑LHXL LH ↑ XHHHH L ↑XHLHLH XXLXXLH L X H X X NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF41x inst_name (Q, QN, C, D, RN, SD, SE); VHDL...................... inst_name: DF41x port map (Q, QN, C, D, RN, SD, SE); Pin Loading Pin Name C D RN SD SE DF411 1.0 1.0 1.0 1.0 2.1 Equivalent Loads DF412 DF414 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.2 DF416 1.0 1.0 1.0 1.0 2.

Published: Mar 12, 2018 |