DF411 - CMOS Gate Array

AMI

General Description

DF41x is a family of static, master-slave, multiplexed scan D flip-flops.

RESET is asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

DF411 cmos gate array by AMI - Datasheet Preview

Datasheet Details

Part number	DF411
Manufacturer	AMI
File Size	46.34 KB
Description	CMOS Gate Array
Datasheet	DF411 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
DF411	FINE OVEN Instruction Manual	Yamato
DF4-19MR20W3M1HF_B11	IGBT	Infineon
DF400R12KE3	IGBT	Infineon
DF40AA120	DIODE	SanRex
DF40AA160	DIODE	SanRex

Other Datasheets by AMI

Part Number	Description
DF412	CMOS Gate Array
DF414	CMOS Gate Array
DF416	CMOS Gate Array
DF401	CMOS Gate Array
DF402	CMOS Gate Array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

')[ ® $0,+* PLFURQ &026 *DWH $UUD Description DF41x is a family of static, master-slave, multiplexed scan D flip-flops. RESET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF41x D C SD SE R Q Q Truth Table C D RN SD SE Q QN ↑HHX LHL ↑LHXL LH ↑ XHHHH L ↑XHLHLH XXLXXLH L X H X X NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF41x inst_name (Q, QN, C, D, RN, SD, SE); VHDL...................... inst_name: DF41x port map (Q, QN, C, D, RN, SD, SE); Pin Loading Pin Name C D RN SD SE DF411 1.0 1.0 1.0 1.0 2.1 Equivalent Loads DF412 DF414 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.2 DF416 1.0 1.0 1.0 1.0 2.