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DL001 - CMOS Gate Array

General Description

DL00x is a family of transparent, unbuffered D latch with active low gate transparency and without SET or RESET.

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Datasheet Details

Part number DL001
Manufacturer AMI
File Size 27.46 KB
Description CMOS Gate Array
Datasheet download datasheet DL001 Datasheet

Full PDF Text Transcription for DL001 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DL001. For precise diagrams, and layout, please refer to the original PDF.

Core Logic '/[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DL00x is a family of transparent, unbuffered D latch with active low gate transparency and without SET or ...

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buffered D latch with active low gate transparency and without SET or RESET. Logic Symbol Truth Table DL00x DQ G GN D Q LLL L HH H X NC NC = No Change HDL Syntax Verilog .................... DL00x inst_name (Q, D, GN); VHDL...................... inst_name: DL00x port map (Q, D, GN); Pin Loading Pin Name D GN Equivalent Loads DL001 DL002 1.0 1.0 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DL001 DL002 4.0 4.0 TBD TBD 6.8 8.6 a. See page 2-15 for power equation. 3-94 Core Logic '/[ ® $0,+*  PLFURQ &026 *DWH $UUD Propagation Delays (ns) C

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