DL011 - CMOS Gate Array

Description

DL011 is a transparent, unbuffered D latch with active low gate transparency.

RESET is active low.

AMI

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Datasheet Details

Part number	DL011
Manufacturer	AMI
File Size	27.81 KB
Description	CMOS Gate Array
Datasheet	DL011 Datasheet
Additional preview pages of the DL011 datasheet.

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Core Logic '/ $0,+* PLFURQ &026 *DWH $UUD Description DL011 is a transparent, unbuffered D latch with active low gate transparency. RESET is active low. Logic Symbol Truth Table Pin Loading DL011 DQ G R RN D GN Q HLLL HH L H H X H NC LXXL NC = No Change Equivalent Load D 1.0 GN 1.0 RN 1.0 ® Equivalent Gates ................ 5.0 HDL Syntax Verilog .................... DL011 inst_name (Q, D, GN, RN); VHDL...................... inst_name: DL011 port map (Q, D, GN, RN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 9.0 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 D Q tPLH tPHL 0.43 0.46 0.

Published: Mar 12, 2018 |