IDTS3 array equivalent, cmos gate array.
IDTS3 is a non-inverting, TTL-level Schmitt input buffer piece.
Logic Symbol
Truth Table
IDTS3
QC P PADM D
PADM QC LL HH
$0,+* PLFURQ &026 *DWH $UUD
Pin Loading
PADM
Load 4.90 pF
HDL Syntax Verilog IDTS3 inst_IDTS3 (QC, PADM); VHDL.. i.
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