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JK031 - CMOS Gate Array

General Description

JK031 is a static, master-slave JK flip-flop.

SET and RESET are asynchronous and active low.

Output is unbuffered and changes state on the rising edge of the clock.

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Datasheet Details

Part number JK031
Manufacturer AMI
File Size 34.65 KB
Description CMOS Gate Array
Datasheet download datasheet JK031 Datasheet

Full PDF Text Transcription for JK031 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for JK031. For precise diagrams, and layout, please refer to the original PDF.

Core Logic -. ® $0,+*  PLFURQ &026 *DWH $UUD Description JK031 is a static, master-slave JK flip-flop. SET and RESET are asynchronous and active low. Output is unb...

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lip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol JK031 J SQ C K R Truth Table RN SN J K L LXX LHXX HLXX HHL L HH L H HHH L HHHH IL = Illegal C Q(n+1) X IL XL XH ↑ NC ↑L ↑H ↑ Q(n) NC = No Change Pin Loading Equivalent Load J 1.0 K 1.0 C 1.0 SN 2.1 RN 2.2 Equivalent Gates ................ 12.0 HDL Syntax Verilog .................... JK031 inst_name (Q, C, J, K, RN, SN); VHDL...................... inst_name: JK031 port map (Q, C, J, K, RN, SN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for pow

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