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Core Logic
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Description MX8x is a family of eight-to-one digital multiplexers.
Logic Symbol
Truth Table
MX8x
S2 S1 S0
|7 |6 |5 |4 Q |3 |2 |1 |0
S2 S1 S0 Q L L L I0 L L H I1 L H L I2 L H H I3 H L L I4 H L H I5 H H L I6 H H H I7
HDL Syntax Verilog .................... MX8x inst_name (Q, I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2); VHDL...................... inst_name: MX8x port map (Q, I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2);
Pin Loading
Pin Name
I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2
MX81 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.6 3.3 2.2
Equivalent Loads
MX82
MX84
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
5.9 5.9
3.5 3.5
2.1 3.3
MX86 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.9 3.5 3.
MX81 Datasheet
