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ODCSIP04 Datasheet Preview

ODCSIP04 Datasheet

CMOS Gate Array

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2'&6,3[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODCSIPxx is a family of 4 to 8 mA, inverting, CMOS-level output buffer pieces with P-channel open-drains (pull-up) and
controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSIPxx
A SL
PADM
A PADM
LH
HZ
Z = High Impedance
HDL Syntax
Verilog .................... ODCSIPxx inst_name (PADM, A);
VHDL...................... inst_name: ODCSIPxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
PADM (pF)
ODCSIP04
4.1
4.94
Power Characteristics
Cell Output Drive (mA)
ODCSIP04
4
ODCSIP08
8
ODCSIP12
12
a. See page 2-15 for power equation.
Load
ODCSIP08
4.1
4.94
ODCSIP12
4.1
4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
190.5
TBD
203.6
TBD
216.8
4-15




AMI

ODCSIP04 Datasheet Preview

ODCSIP04 Datasheet

CMOS Gate Array

No Preview Available !

2'&6,3[[
$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
ODCSIP04
Capacitive Load (pF)
From: A
To: PADM
tZH
15
2.64
ODCSIP08
Capacitive Load (pF)
From: A
To: PADM
tZH
15
1.75
ODCSIP12
Capacitive Load (pF)
From: A
To: PADM
tZH
15
1.60
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
From
A
Delay (ns)
To
PADM
Parameter
tHZ
ODCSIP04
0.78
50 100 200
6.29
11.51
21.93
50 100 200
3.62 6.31 11.65
50 100 200
2.88 4.68 8.26
Cell
ODCSIP08
1.01
ODCSIP12
1.23
®
300 (max)
32.36
300 (max)
16.94
300 (max)
11.86
4-16


Part Number ODCSIP04
Description CMOS Gate Array
Maker AMI
Total Page 2 Pages
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