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ODTHXE24 - CMOS Gate Array

General Description

ODTHXE24 is a high performance, 24 mA, non-inverting, TTL-level, tristate output buffer piece with active low enable.

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Datasheet Details

Part number ODTHXE24
Manufacturer AMI
File Size 18.10 KB
Description CMOS Gate Array
Datasheet download datasheet ODTHXE24 Datasheet

Full PDF Text Transcription for ODTHXE24 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for ODTHXE24. For precise diagrams, and layout, please refer to the original PDF.

2'7+;( ® $0,+*  PLFURQ &026 *DWH $UUD Description ODTHXE24 is a high performance, 24 mA, non-inverting, TTL-level, tristate output buffer piece with active low enab...

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nverting, TTL-level, tristate output buffer piece with active low enable. Logic Symbol Truth Table Pin Loading ODTHXE24 EN A PADM EN A PADM LL L LH H HX Z A EN PADM Load 3.5 eql 6.5 eql 4.93 pF HDL Syntax Verilog .................... ODTHXE24 inst_name (PADM, A, EN); VHDL...................... inst_name: ODTHXE24 port map (PADM, A, EN); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 297.0 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 15 A PADM tPLH tPHL 0.89 1.19 tHZ 1.06 EN PADM tLZ tZH 1.02 0.70

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