AMIS-710616-AS: CIS PCB
4.0 Physical Outline
Table 4-1: Physical Outline
PCB stiffner board
Sensor board connectors
Amplifier PCB board
Amplifier board’s four connectors
PCB stiffner board size
≅355.6mm x 41.3mm x 6.35mm
Size ≈165.1mm x 21.4mm x 1.62mm
Eight analog video outputs
Two I/O connectors
Size ≈ 291.3mm x 76.2mm x 1.6mm
Two inputs: MOLEX 52207-1950
Two outputs: ERNI-594083
See referenced image sensor data sheet
Two PCBs mounted on the stiffner
Used to connect to their respective output
Mounted are eight output amplifiers for each
of the video lines from the sensor boards
5.0 Recommended Operating Conditions (25°C)
Table 5-1: Recommended Operating Conditions at 25°C
VDD 4.5 5.0 5.5
IDD 135 150 165
Video output levels
Video saturation output
Video line saturation output
Input voltage at digital high (input clocks, SP and CP)
VDD-1.0 VDD-.5 VDD+0.3
Input voltage at digital low (input clocks SP and CP)
Clock pulse high duty cycle
Clock high duration
Ns, at 50 percent duty
Typical, tested @ 5.0MHz clock
Minimum, tested @ 6.0MHz clock
(1) Vpavg is a symbol representing the average value of every pixel in the complete line scan. Vp(n) is the pixel amplitude of the nth pixel in a line scan. This
measurement is taken with the image array under a uniform light exposure. The typical output is specified with a uniform input light exposure of 0.5µJ/cm2 from a
blue Led light source.
(2) Two saturated video output levels are specified. One is at the video signal’s output amplifier, VSATA, and the other is at the input of the amplifier. In almost all
applications, because the integration time is usually too short, there is not enough exposure time to saturate the array sensors. Accordingly, each output amplifier
is fixed with a gain of ≅ 4.5.
(3) Freq is generally fixed for any application for the following reasons: One is the exposure time. With a given light power, the exposure time of the sensor can be
related to the clock frequency. The second is the shape of the video output pulse. Because the output video is in pulse charge packets, the signals are processed
on the output video line of the sensors. Hence, the signal shape depends greatly upon the amplifier configurations. Please refer to the referenced AMIS-720639
data sheet. It has some brief outline application notes. Under Note 6 on Page 6, there is a discussion about video pulse shapes. On Page 8, 9 and 10 there are
discussions on the three types of signal output stages.
(4) Duty is the ratio of the clock’s pulse width over its pulse period. Because the video pixel output resets during the clock pulse’s high period and because the reset
requires a finite resetting time, it is recommended to operate the clock duty cycle within the following limits. See the referenced data sheet in Note 3, above.
Noting that the larger the duty, the less the signal amplitude, while too short of a clock pulse will not provide enough video reset time and leaves residual charges,
the recommended duty is 25 percent for frequencies less than 5MHz and 50 percent for frequencies greater than 5MHz.
(5) Tint is determined by the time interval between two start pulses, (SP). Hence, if the SP is generated from a clock count down circuit, it will be directly proportional
to the clock frequency and it will be synchronous with the clock frequency. The longest integration time is determined by the degree of leakage current degradation
that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion and determine the desired
tolerance level for the given system.
(6) Top is a conservative engineering estimate. It is based on measurements of similar CIS modules and simple bench top tests, using heat guns and freeze sprays.
These will be re-measured during the pilot production under the standard QA practices that are under the control of ISO 9000.
AMI Semiconductor – July 06, M-20595-001