AMIS-722402: Contact Image Sensor
3.0 Unique Features
There are six unique features incorporated into the AMIS-722402 which improve the sensor’s performance.
3.1 Pixel-to-pixel Offset Cancellation Circuit
The sensor employs a pixel-to-pixel offset cancellation circuit, which reduces the fixed pattern noise (FPN), and amplifier offsets. In
addition, this innovative circuit design greatly improves the optical linearity and low noise sensitivity.
3.2 Parallel Integrate, Transfer and Hold
The sensor has a parallel integrate, transfer and hold feature, which allows the sensor to be read out while photon integration is taking
place. These features are approached through the use of an integrate-and-hold cell, located at each pixel site. Each pixel’s charge is
read from its storage site as the sensor’s shift register sequentially transfers each pixel’s charge onto a common video line.
3.3 Dual Scan Initiation Inputs, GBST and SI
Each sensor has two scan initiation inputs, the global start pulse (GBST) and the start pulse (SI), which are compatible with standard
3.3V CMOS clocks. These clocks help to reduce the sensor-to-sensor transition FPN by initializing and preprocessing all sensors
simultaneously before they start their readout scan. The internal shift register starts the scan after GBST is clocked in on the falling
edge of the clock input (CLK).
During the first 75 clock cycles following a GBST pulse, all the pixels of all the cascaded sensors cycle through their pre-scan
initialization process that reduces FPN and reset noise.
A sequence of cascaded sensors has a unique first sensor and identically behaving subsequent sensors. The start input control (SIC)
defines whether a sensor will be the first sensor that self-starts the readout of its pixels or will be a subsequent sensor that waits for the
SI before starting the readout of its pixels. With its SIC tied high (Vdd), the first sensor self-starts the readout of its pixels after 75 clock
cycles of delay. With their SIC tied low (ground), all of the subsequent sensors delay their readout of their pixels until after they receive
a SI pulse. Furthermore, the first sensor’s SI is left unconnected, while the subsequent sensors all have their SI connected to the end-
of-scan (SO) of their respective preceding sensor. Just prior to finishing its readout of its pixels, each sensor will send a SO pulse to its
respective subsequent sensor so that its respective subsequent sensor will continue the readout of pixels without a pause or gap in
readout. The external module-level start pulse (SP) is connected to all of the sensors' GBST inputs.
mode, when the first
nine pixels before its
last pixel, in order
its scan, its SO appears on the rising edge
to have a continuous pixel readout between
of 1442nd clock cycle
sensors in a module.
This SO enters as the SI clock of the second and subsequent sensors; hence all subsequent sensors will start their register scan after
each of the preceding sensors completes its scan.
3.4 Power Saving
Each sensor incorporates a power-saving feature when multiple sensors are cascaded together to form a linear imaging array. When a
particular sensor is selected to be read out, the SIC on each sensor selects a unique feature of powering up that sensor’s output
amplifier and powering it down when not selected.
3.5 Common Reference Voltage between Cascaded Sensors
Each sensor has an input/output bias control (VREF), which serves as an offset voltage reference. Each bias control pad is connected
to an internal bias source and tied to its own amplifier’s reference bias input. In operation, these pads on every sensor are connected
together. Each sensor then “shares” the same bias level to maintain a constant bias among all of the sensors.
3.6 Selectable Resolutions of 2400dpi, 1200dpi, 600dpi, 300dpi
The sensor allows for four selectable resolutions; 2400dpi, 1200dpi, 600dpi, and 300dpi, which are controlled by the select resolution 1
and 2 inputs, (SR1, SR2). The following truth details the conditions of the SR1 and SR2 inputs in order to select each resolution, where
low represents the input is connected to ground and a high represents the input connected to Vdd.
AMI Semiconductor – Jan. 06, M-20499-004